Altera Nios II User Manual page 70

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Nios II processor instructions that write to every register (except register 0) initialize
the register file RAM blocks. If shadow register sets are present, this step is performed
for all registers in the shadow register set using the WRPRS instruction.
Nios II processor instructions that write every TLB RAM location initialize the MMU
TLB RAM. This RAM does not require special initialization.
Disabling ECC
Disable ECC in software by writing 0 to CONFIG.ECCEN. Software can re-enable ECC
without reinitializing the ECC-protected RAMs because the ECC parity bits are
written to the RAM blocks even if ECC is disabled.
Handling ECC errors
ECC error exceptions occur when unrecoverable ECC errors are detected. The
software's ability to recover from the ECC error depends on the nature of the error.
Typically, software can recover from an unrecoverable MMU TLB ECC error (2 bit
error) because the TLB is a software-managed cache of the operating system page
tables stored in the main memory (e.g., SDRAM). Software can invalid the TLB entry,
return to the instruction that took the ECC error exception, and execute the TLB's
mishandled code to load a TLB entry from the page tables.
In general, software cannot recover from a register file ECC error (2 bit error) because
the correct value of a register is not known. If the exception handler reads a register
that has a 2 bit ECC error associated with it, another ECC error occurs and an
exception handler loop can occur.
Exception handler loops occur when an ECC error exception occurs in the exception
handler before it is ready to handle nested exceptions. To minimize the occurrence or
exception handler loops, locate the ECC error exception handler code in normal
cacheable memory, ensure that all data accesses are to non-cacheable memory, and
minimize register reading.
The ECC error signals (ecc_event_bus) provide the EEH signal for external logic to
detect a possible exception handler loop and reset the Nios II processor.
Injecting ECC Errors
This section describes the code sequence for injecting ECC errors for each ECC-
protected RAM, assuming the ECC is enabled and interrupts are disabled for the
duration of the code sequence.
Instruction Cache Tag RAM
Ensure all code up to the JMP instruction is in the same instruction cache line or is
■
located in an ITCM.
■ Use a FLUSHI instruction to flush an instruction cache line other than the line
containing the executing code.
■ Use a FLUSHP instruction to flush the pipeline.
Use a WRCTL instruction to set ECCINJ.ICTAG to INJS or INJD (as desired). This
■
setting causes an ECC error to occur on the start of the next line fill.
Nios II Processor Reference Handbook
Chapter 3: Programming Model
Working with ECC
February 2014 Altera Corporation