Altera Nios II User Manual page 155

Chapter 6: Nios II Processor Revision History
Core Revisions
Table 6–3. Nios II/f Core Revisions (Part 3 of 3)
Version Release Date
1.01 September 2004
1.0 May 2004
Nios II/s Core
Table 6–4. Nios II/s Core Revisions (Part 1 of 2)
Version Release Date
13.1 November 2013
11.0 May 2011
10.1 December 2010
10.0 July 2010
9.1 November 2009
9.0 March 2009
8.1 November 2008
8.0 May 2008
7.2 October 2007
7.1 May 2007
7.0 March 2007
6.1 November 2006
6.0 May 2006
5.1 October 2005
5.0 May 2005
February 2014 Altera Corporation
Bug Fixes:
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(1) When a store to memory is followed immediately in the pipeline by a load
from the same memory location, and the memory location is held in the data
cache, the load may return invalid data. This situation can occur in C code
compiled with optimization off (-O0).
(2) The SOPC Builder top-level system module included an extra, unnecessary
output port for systems with very small address spaces.
Initial release of the Nios II/f core.
Added support for enhanced floating-point custom instructions
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No changes.
No changes.
No changes.
No changes.
No changes.
No changes.
Implemented the illegal instruction exception.
Implemented the jmpi instruction.
No changes.
No changes.
No changes.
Cycle count for flushi and initi instructions changes from 1 to 4 cycles.
No changes.
Added optional tightly-coupled memory ports. Designers can add zero to four
■
tightly-coupled instruction master ports.
Made instruction cache optional (previously instruction cache was always
■
present). If the instruction cache is not present, the Nios II core does not have an
instruction master port, and must use a tightly-coupled instruction memory.
Support for HardCopy devices (previous versions required a workaround to
■
support HardCopy devices).
Notes
Notes
Nios II Processor Reference Handbook
6–5