Altera Nios II User Manual page 56

3–16
Software writes to the VPN field when writing a TLB entry. Hardware writes to the VPN
field on a fast TLB miss exception, a TLB permission violation exception, or on a TLB
read operation. The VPN field is not written on any exceptions taken when an
exception is already active, that is, when status.EH is already one.
The tlbacc Register
The tlbacc register is used to access TLB entries and is only available in systems with
an MMU. The tlbacc register holds values that software will write into a TLB entry or
has previously read from a TLB entry. The tlbacc register provides access to only a
portion of a complete TLB entry. pteaddr.VPN and tlbmisc.PID hold the remaining
TLB entry fields.
Table 3–15. tlbacc Control Register Fields
31 30 29 28 27 26 25
IG
Issuing a wrctl instruction to the tlbacc register writes the tlbacc register with the
specified value. If tlbmisc.WE = 1, the wrctl instruction also initiates a TLB write
operation, which writes a TLB entry. The TLB entry written is specified by the line
portion of pteaddr.VPN and the tlbmisc.WAY field. The value written is specified by
the value written into tlbacc along with the values of pteaddr.VPN and tlbmisc.PID.
A TLB write operation also increments tlbmisc.WAY, allowing software to quickly
modify TLB entries.
Issuing a rdctl instruction to the tlbacc register returns the value of the tlbacc
register. The tlbacc register is written by hardware when software triggers a TLB
read operation (that is, when wrctl sets tlbmisc.RD to one).
Table 3–16. tlbacc Control Register Field Descriptions
Field
IG is ignored by hardware and available to hold operating system
IG
specific information. Read as zero but can be written as nonzero.
C is the data cacheable flag. When C = 0, data accesses are
C
uncacheable. When C = 1, data accesses are cacheable.
R is the readable flag. When R = 0, load instructions are not allowed
to access memory. When R = 1, load instructions are allowed to
R
access memory.
W is the writable flag. When W = 0, store instructions are not allowed
to access memory. When W = 1, store instructions are allowed to
W
access memory.
X is the executable flag. When X = 0, instructions are not allowed to
X
execute. When X = 1, instructions are allowed to execute.
G is the global flag. When G = 0, tlbmisc.PID is included in the
TLB lookup. When G = 1, tlbmisc.PID is ignored and only the
G
virtual page number is used in the TLB lookup.
PFN is the physical frame number field. All unused upper bits must
PFN
be zero.
Nios II Processor Reference Handbook
24 23 22 21 20 19 18 17
C R W X G
Description
16 15 14 13 12 11 10 9
PFN
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Chapter 3: Programming Model
8 7 6 5 4 3 2
Access Reset Available
Only with
0
MMU
Only with
0
MMU
Only with
0
MMU
Only with
0
MMU
Only with
0
MMU
Only with
0
MMU
Only with
0
MMU
February 2014 Altera Corporation
Registers
1 0