Altera Nios II User Manual page 82

3–42
1
All undefined opcodes are reserved. The processor does occasionally use some
undefined encodings internally. Executing one of these undefined opcodes does not
trigger an illegal instruction exception. Refer to the
chapter of the Nios II Processor Reference Handbook for information about each specific
Nios II core.
Supervisor-Only Instruction
When your system contains an MMU or MPU and the processor is in user mode
(status.U = 1), executing a supervisor-only instruction results in a supervisor-only
instruction exception. The supervisor-only instructions are initd, initi, eret, bret,
rdctl, and wrctl.
This exception is implemented only in Nios II processors configured to use supervisor
mode and user mode. Refer to
Supervisor-Only Instruction Address
When your system contains an MMU and the processor is in user mode (status.U =
1), attempts to access a supervisor-only instruction address result in a supervisor-only
instruction address exception. Any instruction fetch can cause this exception. For
definitions of supervisor-only address ranges, refer to
This exception is implemented only in Nios II processors that include the MMU.
Supervisor-Only Data Address
When your system contains an MMU and the processor is in user mode (status.U =
1), any attempt to access a supervisor-only data address results in a supervisor-only
data address exception. Instructions that can cause a supervisor-only data address
exception are all loads, all stores, and flushda.
This exception is implemented only in Nios II processors that include the MMU.
Misaligned Data Address
The Nios II processor can check for misaligned data addresses of load and store
instructions and generate an exception when a misaligned data address is
encountered. When your system contains an MMU or MPU, misaligned data address
checking is always on. When no MMU or MPU is present, you have the option to have
the processor check for misaligned data addresses.
f
For information about controlling this option, refer to the
Processor
A data address is considered misaligned if the byte address is not a multiple of the
width of the load or store instruction data width (four bytes for word, two bytes for
half-word). Byte load and store instructions are always aligned so never take a
misaligned address exception.
Nios II Processor Reference Handbook
"Operating Modes" on page 3–1
chapter of the Nios II Processor Reference Handbook.
Chapter 3: Programming Model
Exception Processing
Nios II Core Implementation Details
for more information.
Table 3–2 on page 3–4.
Instantiating the Nios II
February 2014 Altera Corporation