Altera Nios II User Manual page 64

3–24
The LIMIT Field
When the amount of memory reserved for a region is defined by an upper address
limit, the LIMIT field specifies the upper address of the memory region plus one. For
example, to achieve a memory range for byte addresses 0x4000 to 0x4fff with a 256
byte minimum region size, the BASE field of the mpubase register is set to 0x40 (0x4000
>> 8) and the LIMIT field is set to 0x50 (0x5000 >> 8). Because the LIMIT field is one
more bit than the number of bits of the BASE field of the mpubase register, bit 31 of the
mpuacc register is available to the LIMIT field.
The C Flag
The C flag determines the default data cacheability of an MPU region. The C flag only
applies to data regions. For instruction regions, the C bit must be written with 0 and is
always read as 0.
When data cacheability is enabled on a data region, a data access to that region can be
cached, if a data cache is present in the system. You can override the default
cacheability and force an address to noncacheable with an ldio or stio instruction.
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The bit 31 cache bypass feature is supported when the MPU is present. Refer to the
Cache memory section for more information on cache bypass.
The PERM Field
The PERM field specifies the allowed access permissions.
Table 3–29. Instruction Region Permission Values
Table 3–30. Data Region Permission Values
1
Unlisted table values are reserved and must not be used. If you use reserved values,
the resulting behavior is undefined.
The RD Flag
Setting the RD flag signifies that an MPU region read operation should be performed
when a wrctl instruction is issued to the mpuacc register. Refer to the MPU Region
Read and Write Operations section for more information. The RD flag always returns 0
when read by a rdctl instruction.
Nios II Processor Reference Handbook
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Chapter 3: Programming Model
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