Altera Nios II User Manual page 84

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Double TLB Miss
Double TLB miss exceptions are implemented only in Nios II processors that include
the MMU. When a TLB miss exception occurs while software is currently processing
an exception (that is, when status.EH = 1), a double TLB miss exception is generated.
Specifically, whenever the processor cannot find a TLB entry matching the VPN
(optionally extended by a process identifier) and status.EH = 1, the result is a double
TLB miss exception. The most common scenario is that a double TLB miss exception
occurs during processing of a fast TLB miss exception. The processor preserves
register values from the original exception and transfers control to the general
exception handler which processes the newly-generated exception.
There are two kinds of double TLB miss exceptions:
Double TLB miss (instruction)—Any instruction fetch can cause this exception.
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■ Double TLB miss (data)—Load, store, initda, and flushda instructions can cause
this exception.
The general exception handler can inspect either the exception.CAUSE or tlbmisc.D
field to determine which kind of double TLB miss exception occurred.
TLB Permission Violation
TLB permission violation exceptions are implemented only in Nios II processors that
include the MMU. When a TLB entry is found matching the VPN (optionally
extended by a process identifier), but the permissions do not allow the access to
complete, a TLB permission violation exception is generated.
There are three kinds of TLB permission violation exceptions:
■ TLB permission violation (execute)—Any instruction fetch can cause this exception.
■ TLB permission violation (read)—Any load instruction can cause this exception.
TLB permission violation (write)—Any store instruction can cause this exception.
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The general exception handler can inspect the exception.CAUSE field to determine
which permissions were violated.
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The data cache management instructions (initd, initda, flushd, and flushda) ignore
the TLB permissions and do not generate TLB permission violation exceptions.
MPU Region Violation
MPU region violation exceptions are implemented only in Nios II processors that
include the MPU. An MPU region violation exception is generated under any of the
following conditions:
An instruction fetch or data address matched a region but the permissions for that
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region did not allow the action to complete.
An instruction fetch or data address did not match any region.
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The general exception handler reads the MPU region attributes to determine if the
address did not match any region or which permissions were violated.
There are two kinds of MPU region violation exceptions:
MPU region violation (instruction)—Any instruction fetch can cause this exception.
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Nios II Processor Reference Handbook
Chapter 3: Programming Model
Exception Processing
February 2014 Altera Corporation