Altera Nios II User Manual page 73

Chapter 3: Programming Model
Exception Processing
■ Instruction-related exception—Occurs when any of several internal conditions
occurs, as detailed in
exception address you specify in the Nios II processor IP core setup parameters.
The following table columns specify information for the exceptions:
Exception—Gives the name of the exception.
■
■ Type—Specifies the exception type.
■ Available—Specifies when support for that exception is present.
■ Cause—Specifies the value of the CAUSE field of the exception register, for
exceptions that write the exception.CAUSE field.
Address—Specifies the instruction or data address associated with the exception.
■
■ Vector—Specifies which exception vector address the processor passes control to
when the exception occurs.
Table 3–35. Nios II Exceptions (In Decreasing Priority Order) (Part 1 of 2)
Exception
Reset
Hardware break
Processor-only reset
request
Internal interrupt
External nonmaskable
interrupt
External maskable interrupt
ECC TLB error (instruction)
Supervisor-only instruction
address (1)
Fast TLB miss
(instruction) (1)
Double TLB miss
(instruction) (1)
TLB permission violation
(execute) (1)
ECC register file error
MPU region violation
(instruction) (1)
Supervisor-only instruction
Trap instruction
February 2014 Altera Corporation
Table 3–35 on page
Type Available
Reset Always
Break Always
Reset Always
Internal
Interrupt interrupt
controller
External
interrupt
Interrupt
controller
interface
External
interrupt
Interrupt
controller
interface
Instruction-related MMU and ECC
Instruction-related MMU
Instruction-related MMU
Instruction-related MMU
Instruction-related MMU
Instruction-related ECC
Instruction-related MPU
Instruction-related MMU or MPU
Instruction-related Always
3–33. Control is transferred to the
Cause Address
0
—
1
2 (2)
ea–4
— (2)
ea–4
2 (2)
ea–4
18 (2)
ea–4
9 (2)
ea–4
pteaddr.VPN,
12
(2)
ea–4
pteaddr.VPN,
12
(2)
ea–4
pteaddr.VPN,
13
(2)
ea–4
20 (2)
ea–4
16 (2)
ea–4
10 (2)
ea–4
3 (2)
ea–4
Nios II Processor Reference Handbook
3–33
Vector
Reset
Break
Reset
General exception
Requested handler
address (3)
Requested handler
address (3)
General exception
General exception
Fast TLB Miss
exception
General exception
General exception
General exception
General exception
General exception
General exception