Altera Nios II User Manual page 32

2–16
■ Software can guarantee that performance-critical code or data is located in
tightly-coupled memory
No real-time caching overhead, such as loading, invalidating, or flushing memory
■
Physically, a tightly-coupled memory port is a separate master port on the Nios II
processor core, similar to the instruction or data master port. A Nios II core can have
zero, one, or multiple tightly-coupled memories. The Nios II architecture supports
tightly-coupled memory for both instruction and data access. Each tightly-coupled
memory port connects directly to exactly one memory with guaranteed low, fixed
latency. The memory is external to the Nios II core and is located on chip.
Accessing Tightly-Coupled Memory
Tightly-coupled memories occupy normal address space, the same as other memory
devices connected via system interconnect fabric. The address ranges for
tightly-coupled memories (if any) are determined at system generation time.
Software accesses tightly-coupled memory using regular load and store instructions.
From the software's perspective, there is no difference accessing tightly-coupled
memory compared to other memory.
Effective Use of Tightly-Coupled Memory
A system can use tightly-coupled memory to achieve maximum performance for
accessing a specific section of code or data. For example, interrupt-intensive
applications can place exception handler code into a tightly-coupled memory to
minimize interrupt latency. Similarly, compute-intensive digital signal processing
(DSP) applications can place data buffers into tightly-coupled memory for the fastest
possible data access.
If the application's memory requirements are small enough to fit entirely on chip, it is
possible to use tightly-coupled memory exclusively for code and data. Larger
applications must selectively choose what to include in tightly-coupled memory to
maximize the cost-performance trade-off.
f
For additional tightly-coupled memory guidelines, refer to the
Memory with the Nios II Processor
Address Map
The address map for memories and peripherals in a Nios II processor system is design
dependent. You specify the address map in Qsys.
There are three addresses that are part of the processor and deserve special mention:
Reset address
■
■ Exception address
■ Break handler address
Programmers access memories and peripherals by using macros and drivers.
Therefore, the flexible address map does not affect application developers.
Nios II Processor Reference Handbook
tutorial.
Chapter 2: Processor Architecture
Memory and I/O Organization
Using Tightly Coupled
February 2014 Altera Corporation