Altera Nios II User Manual page 53

Chapter 3: Programming Model
Registers
Table 3–8. status Control Register Field Descriptions (Part 2 of 2)
Bit
IL is the interrupt level field. The IL field controls what level of external
maskable interrupts can be serviced. The processor services a maskable
IL
interrupt only if its requested interrupt level is greater than IL.
IH is the interrupt handler mode bit. The processor sets IH to one when it
IH
takes an external interrupt.
EH is the exception handler mode bit. The processor sets EH to one when an
exception occurs (including breaks). Software clears EH to zero when ready
(2) to handle exceptions again. EH is used by the MMU to determine whether a
EH
TLB miss exception is a fast TLB miss or a double TLB miss. In systems
without an MMU, EH is always zero.
U is the user mode bit. When U = 1, the processor operates in user mode.
(2) When U = 0, the processor operates in supervisor mode. In systems without
U
an MMU, U is always zero.
PIE is the processor interrupt-enable bit. When PIE = 0, internal and
maskable external interrupts and noninterrupt exceptions are ignored.
When PIE = 1, internal and maskable external interrupts can be taken,
PIE
depending on the status of the interrupt controller. Noninterrupt exceptions
are unaffected by PIE.
Notes:
(1) The CRS field is read-only. For information about manually changing register sets, refer to the External Interrupt Controller Interface section.
(2) The state where both EH and U are one is illegal and causes undefined results.
(3) When this field is unimplemented, the field value always reads as 0, and the processor behaves accordingly.
(4) When this field is unimplemented, the field value always reads as 1, and the processor behaves accordingly.
The estatus Register
The estatus register holds a saved copy of the status register during nonbreak
exception processing.
Table 3–9. estatus Control Register Fields
31 30 29 28 27 26 25
Reserved
All fields in the estatus register have read/write access. All fields reset to 0.
When the Nios II processor takes an interrupt, if status.eh is zero (that is, the MMU
is in nonexception mode), the processor copies the contents of the status register to
estatus.
1
If shadow register sets are implemented, and the interrupt requests a shadow register
set, the Nios II processor copies status to sstatus, not to estatus.
f
For details about the sstatus register, refer to The sstauts Register section.
February 2014 Altera Corporation
Description
24 23 22 21 20 19 18 17
PRS
16 15 14 13 12 11 10 9
CRS
Access Reset Available
EIC
Read/Write 0 interface
only
EIC
Read/Write 0 interface
only
MMU or
Read/Write 0 ECC
only
MMU or
Read/Write 0 MPU
only
Read/Write 0 Always
8 7 6 5 4 3 2
IL
Nios II Processor Reference Handbook
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