Altera Nios II User Manual page 26

2–10
Exception Controller
The Nios II architecture provides a simple, nonvectored exception controller to handle
all exception types. Each exception, including internal hardware interrupts, causes the
processor to transfer execution to an exception address. An exception handler at this
address determines the cause of the exception and dispatches an appropriate
exception routine.
Exception addresses are specified with the Qsys Nios II Processor parameter editor.
All exceptions are precise. Precise means that the processor has completed execution
of all instructions preceding the faulting instruction and not started execution of
instructions following the faulting instruction. Precise exceptions allow the processor
to resume program execution once the exception handler clears the exception.
EIC Interface
An EIC provides high performance hardware interrupts to reduce your program's
interrupt latency. An EIC is typically used in conjunction with shadow register sets
and when you need more than the 32 interrupts provided by the Nios II internal
interrupt controller.
The Nios II processor connects to an EIC through the EIC interface. When an EIC is
present, the internal interrupt controller is not implemented; Qsys connects interrupts
to the EIC.
The EIC selects among active interrupts and presents one interrupt to the Nios II
processor, with interrupt handler address and register set selection information. The
interrupt selection algorithm is specific to the EIC implementation, and is typically
based on interrupt priorities. The Nios II processor does not depend on any specific
interrupt prioritization scheme in the EIC.
For every external interrupt, the EIC presents an interrupt level. The Nios II processor
uses the interrupt level in determining when to service the interrupt.
Any external interrupt can be configured as an NMI. NMIs are not masked by the
status.PIE bit, and have no interrupt level.
An EIC can be software-configurable.
1
When the EIC interface and shadow register sets are implemented on the Nios II core,
you must ensure that your software is built with the Nios II EDS version 9.0 or higher.
Earlier versions have an implementation of the eret instruction that is incompatible
with shadow register sets.
f
For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the
Embedded Peripherals IP User
For details about EIC usage, refer to "Exception Processing" in the
chapter of the Nios II Processor Reference Handbook.
Nios II Processor Reference Handbook
Guide.
Chapter 2: Processor Architecture
Exception and Interrupt Controllers
Programming Model
February 2014 Altera Corporation