Altera Nios II User Manual page 116

4–12
■ TLB entries—Specifies the number of entries in the translation lookaside buffer
(TLB).
TLB Set-Associativity—Specifies the number of set-associativity ways in the TLB.
■
Micro DTLB entries—Specifies the number of entries in the micro data TLB.
■
■ Micro ITLB entries—Specifies the number of entries in the micro instruction TLB.
f
For information about the MMU, refer to the
Processor Reference Handbook.
For specifics on the Nios II/f core, refer to the
chapter of the Nios II Processor Reference Handbook.
MPU
When Include MPU on the Core Nios II tab is on, the MPU settings on the MMU and
MPU Settings tab provide the following options for the MPU in the Nios II/f core.
Use Limit for region range—Controls whether the amount of memory in the
■
region is defined by size or by upper address limit. When on, the amount of
memory is based on the given upper address limit. When off, the amount of
memory is based on the given size.
■ Number of data regions—Specifies the number of data regions to allocate.
Allowed values range from 2 to 32.
■ Minimum data region size—Specifies the minimum data region size. Allowed
values range from 64 bytes to 1 MB and must be a power of two.
Number of instruction regions—Specifies the number of instruction regions to
■
allocate. Allowed values range from 2 to 32.
■ Minimum instruction region size—Specifies the minimum instruction region
size. Allowed values range from 64 bytes to 1 MB and must be a power of two.
1
The maximum region size is the size of the Nios II instruction and data addresses
automatically determined when the Nios II system is generated in Qsys. Maximum
region size is based on the address range of slaves connected to the Nios II instruction
and data masters.
f
For information about the MPU, refer to the
Processor Reference Handbook.
For specifics on the Nios II/f core, refer to the
chapter of the Nios II Processor Reference Handbook.
Nios II Processor Reference Handbook
Chapter 4: Instantiating the Nios II Processor
MMU and MPU Settings Tab
Programming Model chapter of the Nios II
Nios II Core Implementation Details
Programming Model chapter of the Nios II
Nios II Core Implementation Details
February 2014 Altera Corporation