Document Revision History - Altera Nios II User Manual

5–22
Exception Handling
The Nios II/e core supports the following exception types:
■ Internal hardware interrupt
■ Software trap
■ Illegal instruction
■ Unimplemented instruction
JTAG Debug Module
The Nios II/e core supports the JTAG debug module to provide a JTAG interface to
software debugging tools. The JTAG debug module on the Nios II/e core does not
support hardware breakpoints or trace.

Document Revision History

Table 5–18
Table 5–18. Document Revision History (Part 1 of 2)
Date Version
February 2014 13.1.0
May 2011 11.0.0
December 2010 10.1.0
July 2010 10.0.0
November 2009 9.1.0
March 2009 9.0.0
November 2008 8.1.0
May 2008 8.0.0
October 2007 7.2.0
May 2007 7.1.0
March 2007 7.0.0
November 2006 6.1.0
May 2006 6.0.0
October 2005 5.1.0
May 2005 5.0.0
December 2004 1.2
Nios II Processor Reference Handbook
lists the revision history for this document.
Added information on ECC support
■
Removed HardCopy support information
■
Removed references to SOPC Builder
■
Maintenance release.
Maintenance release.
Updated device support nomenclature
■
Corrected HardCopy support information
■
Added external interrupt controller interface information.
■
Added shadow register set information.
■
Maintenance release.
Maintenance release.
Added text for MMU and MPU.
Added jmpi instruction to tables.
Added table of contents to Introduction section.
■
Added Referenced Documents section.
■
Add preliminary Cyclone III device family support
Add preliminary Stratix III device family support
Performance for flushi and initi instructions changes from 1 to 4 cycles for Nios II/s
and Nios II/f cores.
Maintenance release.
Updates to Nios II/f and Nios II/s cores. Added tightly-coupled memory and new data cache
options. Corrected cycle counts for shift/rotate operations.
Updates to Multiply and Divide Performance section for Nios II/f and Nios II/s cores.
Chapter 5: Nios II Core Implementation Details
Document Revision History
Changes
February 2014 Altera Corporation