Altera Nios II User Manual page 273

Chapter 8: Instruction Set Reference
Instruction Set Reference
stb / stbio
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31 30 29 28 27 26 25
A
31 30 29 28 27 26 25
A
February 2014 Altera Corporation
Mem8[rA + σ (IMM16)] ← rB
stb rB, byte_offset(rA)
stbio rB, byte_offset(rA)
stb r6, 100(r5)
Computes the effective byte address specified by the sum of rA and the instruction's signed
16-bit immediate value. Stores the low byte of rB to the memory byte specified by the effective
address.
In processors with a data cache, this instruction may not generate an Avalon-MM bus cycle to
noncache data memory immediately. Use the stbio instruction for peripheral I/O. In
processors with a data cache, stbio bypasses the cache and is guaranteed to generate an
Avalon-MM data transfer. In processors without a data cache, stbio acts like stb.
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
24 23 22 21 20 19 18 17
B
Instruction format for stb
24 23 22 21 20 19 18 17
B
Instruction format for stbio
store byte to memory or I/O peripheral
7..0
16 15 14 13 12 11 10 9
IMM16
16 15 14 13 12 11 10 9
IMM16
8 7 6 5 4 3 2 1
0x05
8 7 6 5 4 3 2 1
0x25
Nios II Processor Reference Handbook
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