Altera Nios II User Manual page 94

3–54
2. Transfers program execution to the address in the ea register (r29) in the register
set specified by the original value of status.CRS.
1
The eret instruction can cause the processor to exit NMI mode. However, it cannot
make the processor enter NMI mode. In other words, if status.NMI is 0 and
estatus.NMI (or sstatus.NMI) is 1, after an eret, status.NMI is still 0. This restriction
prevents the processor from accidentally entering NMI mode.
1
When the EIC interface and shadow register sets are implemented on the Nios II core,
you must ensure that your software, including ISRs, is built with the version of the
GCC compiler included in Nios II EDS version 9.0 or later. Earlier versions have an
implementation of the eret instruction that is incompatible with shadow register sets.
Return Address Considerations
The return address requires some consideration when returning from exception
processing routines. After an exception occurs, ea contains the address of the
instruction following the point where the exception occurred.
When returning from instruction-related exceptions, execution must resume from the
instruction following the instruction where the exception occurred. Therefore, ea
contains the correct return address.
On the other hand, hardware interrupt exceptions must resume execution from the
interrupted instruction itself. In this case, the exception handler must subtract 4 from
ea to point to the interrupted instruction.
Masking and Disabling Exceptions
The Nios II processor provides several methods for temporarily turning off some or
all exceptions from software. The available methods depend on the hardware
configuration. This section discusses all potentially available methods.
Disabling Maskable Interrupts
Software can disable and enable maskable interrupts with the status.PIE bit. When
PIE = 0, maskable interrupts are ignored. When PIE = 1, internal and maskable
external interrupts can be taken, depending on the status of the interrupt controller.
Masking Interrupts with an External Interrupt Controller
Typical EIC implementations allow system software to mask individual interrupts.
The method of masking individual interrupts is implementation-specific.
The status.IL field controls what level of external maskable interrupts can be
serviced. The processor services a maskable interrupt only if its requested interrupt
level is greater than status.IL.
An ISR can make run-time adjustments to interrupt nesting by manipulating
status.IL. For example, if an ISR is running at level 5, to temporarily allow
pre-emption by another level 5 interrupt, it can set status.IL to 4.
To enable all external interrupts, set status.IL to 0. To disable all external interrupts,
set status.IL to 63.
Nios II Processor Reference Handbook
Chapter 3: Programming Model
Exception Processing
February 2014 Altera Corporation