Altera Nios II User Manual page 24

2–8
Table 2–3. Floating Point Custom Instruction 2 Operation Summary (Part 2 of 2)
Operation (1) N
fnegs 225
fabss 224
Notes:
(1) These names match the names of the corresponding GCC command-line options except for round, which GCC does not support.
(2) Specifies the 8 bit fixed custom instruction for the operation.
(3) Specifies the number of cycles required to execute the instruction. A combinatorial custom instruction takes 1 cycle. A multi-cycle custom
instruction requires at least 2 cycles. An N-cycle multi-cycle custom instruction has N - 2 register stages inside the custom instruction because
the Nios II processor registers the result from the custom instruction and allows another cycle for g wire delays in the source operand bypass
multiplexers. The number of cycles does not include the extra cycles (maximum of 2) that an instruction following the multi-cycle custom
instruction is stalled by the Nios II/f if the instruction uses the result within 2 cycles. These extra cycles occur because multi-cycle instructions
are late result instructions.
(4) Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating-point functions with the equivalent custom instruction even
though it has -mcustom-<operation> command-line options and pragma support for these operations. Instead, the custom instruction must
be invoked directly using the GCC __builtin_custom_* facility. The Floating Point Custom Instruction 2 component includes a C header file
that provides the required #define macros to invoke the custom instruction directly.
In Qsys, the Floating Point Hardware 2 component is under Embedded Processors
on the Component Library tab.
The Nios II Software Build Tools (SBT) include software support for the Floating Point
Custom Instruction 2 component. When the Floating Point Custom Instruction 2
component is present in hardware, the Nios II compiler compiles the software codes
to use the custom instructions for floating point operations.
Floating Point Custom Instruction Component
The Floating Point Hardware component supports addition, subtraction,
multiplication, and (optionally) division. The Floating Point Hardware parameter
editor allows you to omit the floating-point division hardware for cases in which code
running on your hardware design does not make heavy use of floating-point division.
When you omit the floating-point divide instruction, the Nios II compiler implements
floating-point division in software.
In Qsys, the Floating Point Hardware component is under Embedded Processors on
the Component Library tab.
The Nios II floating-point custom instructions are based on the Altera
megafunctions: ALTFP_MULT, ALTFP_ADD_SUB, and ALTFP_DIV.
f
For information about each individual floating-point megafunction, including
acceleration factors and device resource usage, refer to the megafunction user guides,
available on the
The Nios II software development tools recognize C code that takes advantage of the
floating-point instructions present in the processor core. When the floating-point
custom instructions are present in your target hardware, the Nios II compiler
compiles your code to use the custom instructions for floating-point operations and
the newlib math library.
Nios II Processor Reference Handbook
Cycles (3) Result
1 -a
1 |a|
IP and Megafunctions
Chapter 2: Processor Architecture
Subnormal Rounding
Supported None
Supported None
literature page of the Altera website.
February 2014 Altera Corporation
Arithmetic Logic Unit
GCC Inference
-a
fabsf()
®
floating-point