Altera Nios II User Manual page 88

3–48
Exceptions and Processor Status
Table 3–37
exception processing actions performed by hardware. For systems with an MMU,
status.EH indicates whether or not exception processing is already in progress. When
status.EH = 1, exception processing is already in progress and the states of the
exception registers are preserved to retain the original exception states.
Table 3–37. Nios II Processor Status After Taking Exception
status.EH==1
Processor Status
Register or Field
RRS==0
(3)
(5)
pteaddr.VPN
(3) No change
status.PRS
pc
(10) (11)
sstatus
(11) No change
estatus
No change
ea
(2)
tlbmisc.D
(2)
tlbmisc.DBL
(2)
tlbmisc.PERM
(2)
tlbmisc.BAD
status.PIE
(2)
status.EH
(21)
status.IH
(21)
status.NMI
(21)
status.IL
status.RSIE
(3) (21)
(3)
status.CRS
(2)
status.U
Nios II Processor Reference Handbook
lists all changes to the Nios II processor state as a result of nonbreak
System Status Before Taking Exception
External Interrupt Asserted
(2) status.EH==0
RRS!=0 RRS==0
No change
status.CRS
RHA
No change
status
(7)
return address
No change
No change
No change
No change
(18)
config.ANI
No change
1
RNMI
RIL
0
RRS
(1) Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1
TLB Miss
RRS!=0
(3) (7)
Fast TLB
General
exception
exception
vector (8)
status
(7) (12)
No change
(13) No change
0 (22)
Chapter 3: Programming Model
Exception Processing
status.EH==0
No TLB Miss
(4)
TLB
No TLB
Permission
Permission
Violation
Violation
(4)
VPN (6) No change
No change
General exception
vector vector (3)
(9)
No change
(7)
status
return address
(14)
(15)
(16)
(17)
0 (19)
1 (20)
No change
No change
No change
No change
No change
February 2014 Altera Corporation