Altera Nios II User Manual page 45

Chapter 3: Programming Model
Memory Management Unit
Physical Memory Address Space
The 4-GB physical memory is divided into low memory and high memory. The lowest
½ GB of physical address space is low memory. The upper 3½ GB of physical address
space is high memory.
Figure 3–1. Division of Physical Memory
High physical memory can only be accessed through the TLB. Any physical address
in low memory (29-bits or less) can be accessed through the TLB or by bypassing the
TLB. When bypassing the TLB, a 29-bit physical address is computed by clearing the
top three bits of the 32-bit virtual address.
1
To function correctly, the base physical address of all exception vectors (reset, general
exception, break, and fast TLB miss) must point to low physical memory so that
hardware can correctly map their virtual addresses into the kernel partition. The
Nios II Processor parameter editor in Qsys prevents you from choosing an address
outside of low physical memory.
Data Cacheability
Each partition has a rule that determines the default data cacheability property of
each memory access. When data cacheability is enabled on a partition of the address
space, a data access to that partition can be cached, if a data cache is present in the
system. When data cacheability is disabled, all access to that partition goes directly to
the Avalon switch fabric. Bit 31 is not used to specify data cacheability, as it is in
Nios II cores without MMUs. Virtual memory partitions that bypass the TLB have a
default data cacheability property, as described in the abmove table, Virtual Memory
Partitions
controlled by the TLB on a per-page basis.
Non-I/O load and store instructions use the default data cacheability property. I/O
load and store instructions are always noncacheable, so they ignore the default data
cacheability property.
February 2014 Altera Corporation
0xFFFFFFFF
3.5 GByte High Memory
0x20000000
0x1FFFFFFF
0.5 GByte Low Memory
0x00000000
. For partitions that are mapped through the TLB, data cacheability is
Accessed only via TLB
Accessed directly or via TLB
Nios II Processor Reference Handbook
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