Strongarm Sa-1110 To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

4 StrongARM SA-1110 to S1D13706 Interface

4.1 Hardware Description

SA-1110
nWE
nCAS1
nOE
nCS4
RDY
A17
nCAS0
A[16:1]
D[15:0]
SDCLK2
Note:
When connecting the S1D13706 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of SA-1110 to S1D13706 Interface
Interfacing to the Intel StrongARM SA-1110 Microprocessor
Issue Date: 02/06/26
The SA-1110 microprocessor provides a variable latency I/O interface that can be used to
support an external LCD controller. By using the Generic # 2 Host Bus Interface, no glue
logic is required to interface the S1D13706 and the SA-1110.
A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.
BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and should
be tied high (connected to HIO V
The following diagram shows a typical implementation of the SA-1110 to S1D13706
interface.
).
DD
HIO V
DD
Pull-up
System RESET
Page 13
S1D13706
BS#
RD/WR#
WE0#
WE1#
RD#
CS#
WAIT#
M/R#
AB0
AB[16:1]
DB[15:0]
CLKI
RESET#
S1D13706
X31B-G-019-02