Analog Devices ADuCM356 Reference Manual page 6

Reference Manual
TABLE OF CONTENTS
SRAM................................................................ 200
SRAM Features..............................................200
Instruction vs. Data SRAM............................. 200
SRAM Retention in Hibernate Mode.............. 201
SRAM Initialization......................................... 201
Cache................................................................ 202
Initialization in Cache and Instruction SRAM. 202
Programming Guidelines................................202
Register Summary: Cache (FLCC)....................203
Register Details: Cache (FLCC)........................ 204
Cache Status Register................................... 204
Cache Setup Register.................................... 204
Cache Key Register....................................... 204
Silicon Identification...........................................205
Register Summary: System (Digital Die)........... 206
Register Details: System (Digital Die)............... 207
Analog Devices Identification (Digital Die)
Register........................................................ 207
Chip Identifier (Digital Die) Register............... 207
Serial Wire Debug Enable Register................207
Analog Devices Identification (Analog Die)
Register........................................................ 207
Chip Identification (Analog Die) Register....... 207
16-Bit Scratch Register to Test Interdie
Communications Register............................ 208
Digital Inputs and Outputs................................. 209
Digital Inputs and Outputs Features...............209
Digital Inputs and Outputs Overview.............. 209
Digital Inputs and Outputs Operation............. 209
Interrupts........................................................ 210
Digital Die Port Mux........................................211
AFE Die Digital Port Mux................................211
Register Summary: Digital Inputs and Outputs. 212
Register Details: Digital Inputs and Outputs......214
GPIO Port Configuration Registers................ 214
GPIO Port Output Enable Registers...............214
GPIO Port Input/Output Pull-Up Enable
Registers...................................................... 214
GPIO Port Input Path Enable Registers......... 215
GPIO Port Registered Data Input Registers...215
GPIO Port Data Output Registers.................. 215
GPIO Port Data Output Set Registers............215
GPIO Port Data Output Clear Registers.........217
GPIO Port Pin Toggle Registers.....................217
GPIO Port Interrupt Polarity Registers........... 217
GPIO Port Interrupt A Enable Registers.........217
GPIO Port Interrupt B Enable Registers.........218
GPIO Port Interrupt Status Registers............. 218
GPIO Port Drive Strength Select Registers....218
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AFE GPIO Port Configuration Register.......... 218
AFE GPIO Port Output Enable Register........ 219
AFE GPIO Port Output Pull-Up and Pull-
Down Enable Register..................................219
AFE GPIO Port Input Path Enable Register...219
AFE GPIO Port Registered Data Input...........219
AFE GPIO Port Data Output Register............ 219
AFE GPIO Port Data Output Set Register......220
AFE GPIO Port Data Output Clear Register.. 220
AFE GPIO Port Pin Toggle Register...............220
2
I C Serial Interface............................................ 221
2
I C Features................................................... 221
2
I C Overview.................................................. 221
2
I C Operation................................................. 221
2
I C Operating Modes......................................223
2
Register Summary: I C......................................226
2
Register Details: I C.......................................... 227
Initiator Control Register.................................227
Initiator Status Register.................................. 227
Initiator Receive Data Register.......................228
Initiator Transmit Data Register......................228
Initiator Receive Data Count Register............ 229
Initiator Current Receive Data Count
Register........................................................ 229
First Initiator Address Byte Register...............229
Second Initiator Address Byte Register..........229
Serial Clock Period Divisor Register.............. 230
Target Control Register.................................. 230
2
Target I C Status, Error, and IRQ Register.... 231
Target Receive Register................................. 232
Target Transmit Register................................ 232
Hardware General Call ID Register................232
First Target Address Device ID Register........ 232
Second Target Address Device ID Register... 234
Third Target Address Device ID Register....... 234
Fourth Target Address Device ID Register.....234
Initiator and Target FIFO Status Register.......234
Initiator and Target Shared Control Register.. 235
Automatic Stretch Control for Initiator and
Target Mode Register................................... 235
Serial Peripheral Interfaces............................... 237
SPI Features.................................................. 237
SPI Overview..................................................237
SPI Operation.................................................237
SPI Transfer Initiation.....................................238
SPI Interrupts................................................. 240
SPI Wire-OR'ed Mode....................................240
SPI CSERR Condition....................................241
SPI DMA.........................................................241
ADuCM356
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