Lpdac0 Data Out Register; Lpdac0 Switch Control Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS
Table 112. Bit Descriptions for LPTIASW1 (Continued)
Bits Bit Name Settings
5 SW5
4 SW4
3 SW3
2 SW2
1 SW1
0 SW0

LPDAC0 DATA OUT REGISTER

Address: 0x400C2120, Reset: 0x00000000, Name: LPDACDAT0
Table 113. Bit Descriptions for LPDACDAT0
Bits Bit Name Settings
[31:18] Reserved
[17:12] DACIN6
111111 2.366 V.
[11:0] DACIN12
0xFFF 2.4 V.

LPDAC0 SWITCH CONTROL REGISTER

Address: 0x400C2124, Reset: 0x00000000, Name: LPDACSW0
Table 114. Bit Descriptions for LPDACSW0
Bits Bit Name Settings
[31:6] Reserved
5 LPMODEDIS
4 SW4
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Description
1 Close switch.
SW5 Switch Control Active High. Close to connect external capacitor or R
RC1_0 and RC1_1 pins.
0 Open switch.
1 Close switch.
SW4 Switch Control Active High.
0 Open switch.
1 Close switch.
SW3 Switch Control Active High.
0 Open switch.
1 Close switch.
SW2 Switch Control Active High.
0 Open switch.
1 Close switch.
SW1 Switch Control Active High.
0 Open switch.
1 Close switch.
SW0 Switch Control Active High.
0 Open switch.
1 Close switch.
Description
Reserved.
6-Bit Value, 1 LSB = 34.375 mV. A low-power DAC0 6-bit output data register value between 0 and 0x3F
is expected to set 6-bit output voltage.
0 0.2 V.
12-Bit Value, 1 LSB = 537 μV. A low-power DAC0 12-bit output data register value between 0 and 0xFFF
is expected to set 12-bit output voltage.
0 0.2 V.
Description
Reserved.
Switch Control. Controls switches connected to the output of low-power DAC0.
0 Switches connected to output of low-power DAC configured via LPDACCON0, Bit 5. Default.
1 Overrides LPDACCON0, Bit 5. Switches connected to the low-power DAC0 output are controlled
via LPDACSW0, Bits[4:0].
LPDAC0 SW4 Control.
ADuCM356
Reset
resistor between the 0x0
TIA
0x0
0x0
0x0
0x0
0x0
Reset
0x0
0x0
0x0
Reset
0x0
0x0
0x0
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Access
R/W
R/W
R/W
R/W
R/W
R/W
Access
R
R/W
R/W
Access
R
R/W
R/W