Gpio Clock Mux Select To Gpio1 Pin Register; Key Protection For Clkcon0 Register; Clock Control Of Low-Power Tia Chop, Watchdog, And Wake-Up Timers Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: CLOCK ARCHITECTURE
Table 13. Bit Descriptions for CLKSEL (Continued)
Bits Bit Name Settings
[1:0] SYSCLKSEL

GPIO CLOCK MUX SELECT TO GPIO1 PIN REGISTER

Address: 0x400C041C, Reset: 0x0000, Name: GPIOCLKMUXSEL
Select which digital clock is output to GPIO1 for observation.
Table 14. Bit Descriptions for GPIOCLKMUXSEL
Bits Bit Name
[15:3] Reserved
[2:0] SEL

KEY PROTECTION FOR CLKCON0 REGISTER

Address: 0x400C0420, Reset: 0x0000, Name: CLKCON0KEY
This register provides key protection for the CLKCON0 register.
Table 15. Bit Descriptions for CLKCON0KEY
Bits Bit Name Settings
[15:0] KEY

CLOCK CONTROL OF LOW-POWER TIA CHOP, WATCHDOG, AND WAKE-UP TIMERS REGISTER

Address: 0x400C0A70, Reset: 0x0000, Name: CLKEN0
Table 16. Bit Descriptions for CLKEN0
Bits Bit Name
[15:3] Reserved
2 TIACHPDIS
analog.com
Description
1 External high frequency crystal (XTAL) clock.
10 Internal low frequency oscillator clock. Not recommended.
11 External clock.
Select System Clock Source. To configure the GPIO1 pin for an external clock,
pADI_AGPIO2->CON |= 3<<2; // EXT_CLK pADI_AGPIO2->IEN |=
1<<1; //AGPIO2.1(PWM1) input
0 Internal high frequency oscillator clock.
1 External high frequency XTAL clock.
10 Internal low frequency oscillator clock. Not recommended.
11 External clock.
Settings Description
Reserved.
Configure Clock Mux Out to GPIO1.
0 System clock.
1 Power gate low frequency clock.
10 PCLK.
11 Wake-up timer (WUT) on analog die clock.
100 GPT0 clock.
101 GPT1 clock.
110 ADC clock.
111 ADC control clock.
Description
Key to Allow Read and Write Access to the CLKCON0 Register. Write 0xA815 to this register before
accessing CLKCON0.
Settings Description
Reserved.
TIA Chop Clock Disable.
0 Turn on TIA chop clock.
1 Turn off TIA chop clock.
ADuCM356
Reset Access
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 W
Reset Access
0x0 R
0x1 R/W
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