Initiator And Target Shared Control Register; Automatic Stretch Control For Initiator And Target Mode Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: I
Table 301. Bit Descriptions for FSTAT (Continued)
Bits Bit Name Settings
[3:2] SRXF
[1:0] STXF

INITIATOR AND TARGET SHARED CONTROL REGISTER

Address: 0x40003050, Reset: 0x0000, Name: SHCTL
Table 302. Bit Descriptions for SHCTL
Bits Bit Name Settings
[15:1] Reserved
0 RST

AUTOMATIC STRETCH CONTROL FOR INITIATOR AND TARGET MODE REGISTER

Address: 0x40003058, Reset: 0x0000, Name: ASTRETCH_SCL
Table 303. Bit Descriptions for ASTRETCH_SCL
Bits Bit Name Settings
[15:10] Reserved
9 SLVTMO
8 MSTTMO
[7:4] SLV
0001 to 1110 Automatic target clock stretching enabled. The timeout period is defined as follows:
analog.com
2
C
Description
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Target Receive FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Target Transmit FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Description
Reserved.
Reset LINEBUSY. Setting this bit resets the LINEBUSY status bit (Bit 10 in the MSTAT register).
0 No effect.
2
1 Reset the I C start and stop detection circuits.
Description
Reserved.
Stretch Timeout Status Bit for Target.
0 Cleared when this bit is read.
1 Set when target automatic stretch mode has timed out.
Stretch Timeout Status Bit for Initiator.
0 Cleared when this bit is read.
1 Set when initiator automatic stretch mode has timed out.
Automatic Stretch Mode Control for Target. These bits control automatic stretch mode for target
operation. These bits allow the target to hold the I2C_SCL line low and gain more time to service an
interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the
target indefinitely holds I2C_SCL low. As a target transmitter, I2C_SCL is automatically stretched from
the negative edge of I2C_SCL (if the target transmit FIFO is empty) before sending an acknowledge or
a no acknowledge for an address byte, or before sending data for a data byte. Stretching stops when
the target transmit FIFO is no longer empty or a timeout occurs. As a target receiver, the I2C_SCL clock
is automatically stretched from the negative edge of I2C_SCL before sending an acknowledge or a no
acknowledge when the target receive FIFO is full. Stretching stops when the target receive FIFO is no
longer in an overflow condition or a timeout occurs.
0000 Automatic target clock stretching disabled.
ADuCM356
Reset Access
0x0 R
0x0 R
Reset Access
0x0000 R/W
0x0 W
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R/W
Rev. A | 235 of 312