Dft Result, Real Part Register; Dft Result, Imaginary Part Register; Sinc2 And Supply Rejection Filter Result Register; Temperature Sensor 0 Result Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: ADC CIRCUIT

DFT RESULT, REAL PART REGISTER

Address: 0x400C2078, Reset: 0x00000000, Name: DFTREAL
Table 66. Bit Descriptions for DFTREAL
Bits Bit Name Settings
[31:18] Reserved
[17:0] DATA

DFT RESULT, IMAGINARY PART REGISTER

Address: 0x400C207C, Reset: 0x00000000, Name: DFTIMAG
Table 67. Bit Descriptions for DFTIMAG
Bits Bit Name Settings
[31:18] Reserved
[17:0] DATA

SINC2 AND SUPPLY REJECTION FILTER RESULT REGISTER

Address: 0x400C2080, Reset: 0x00000000, Name: SINC2DAT
Table 68. Bit Descriptions for SINC2DAT
Bits Bit Name Settings
[31:16] Reserved
[15:0] RESULT

TEMPERATURE SENSOR 0 RESULT REGISTER

Address: 0x400C2084, Reset: 0x00000000, Name: TEMPSENSDAT0
Table 69. Bit Descriptions for TEMPSENSDAT0
Bits Bit Name
[31:16] Reserved
[15:0] DATA

ANALOG CAPTURE INTERRUPT ENABLE REGISTER

Address: 0x400C2088, Reset: 0x00000000, Name: ADCINTIEN
Table 70. Bit Descriptions for ADCINTIEN
Bits Bit Name
[31:8] Reserved
7 MEANIEN
6 ADCDELTAFAILIEN
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Description
Reserved.
DFT Real. DFT hardware accelerator returns a complex number. This register returns the 18-bit real part
of the complex number from the DFT result. The DFT result is represented in twos complement.
Description
Reserved.
DFT Imaginary. DFT hardware accelerator returns a complex number. This register returns the 18-bit
imaginary part of the complex number from the DFT result. DFT result is represented in twos
complement.
Description
Reserved.
Sinc2 and Low-Pass Filter Result. Sinc2 and power supply rejection filter, ADC output result. Data output
from 50 Hz or 60 Hz rejection filter. When new data is available, ADCINTSTA, Bit 2 is set to 1.
Settings Description
Reserved.
Temperature Sensor. ADC temperature sensor Channel 0 result.
Settings Description
Reserved.
Mean Interrupt. Mean result ready interrupt enable.
0 Interrupt disabled.
1 Interrupt enabled.
ADC Delta Value Check Fail Interrupt Enable. When set, this bit generates an interrupt if the
difference between two consecutive ADC samples is greater than the value in the ADC delta
range.
0 Interrupt disabled.
ADuCM356
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
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