Analog Devices ADuCM356 Reference Manual page 168

Reference Manual
DMA CONTROLLER
count. The user can check the N count to determine how many data
transfers occurred before the bus error.
When the controller fetches an invalid descriptor, the faulty channel
is automatically disabled, and the corresponding status bit in the
INVALIDDESC_CLR register is set. If the DMA error is enabled in
NVIC, the error also generates an interrupt.
Address Calculation
The DMA controller calculates the source read address based
on the content of SRC_END_PTR, the source address increment
setting in CHNL_CFG, and the current value of CHNL_CFG,
Bits[13:4] (N_MINUS_1). Similarly, the destination write address
is calculated based on the content of DST_END_PTR, the desti-
nation address increment setting in CHNL_CFG, and the current
value of CHNL_CFG, Bits[13:4]. In the following code examples,
N_MINUS_1 is the number of configured transfers minus 1 for that
channel:
Source Read Address = SRC_END_PTR − (N_MINUS_1
<< (SRC_INC)) for SRC_INC = 0, 1, 2
Source Read Address = SRC_END_PTR for SRC_INC
= 3
Destination Write Address = DST_END_PTR −
(N_MINUS_1 << (DST_INC)) for DST_INC = 0, 1,
2
Destination Write Address = DST_END_PTR for
DST_INC = 3
Address Decrement
The address decrement can be enabled for source and destination
addresses. Source address decrement can be enabled for channels
by setting the appropriate bits in the SRCADDR_SET register. Sim-
ilarly, destination address decrement can be enabled for channels
by setting the required bits in the DSTADDR_SET register. The
analog.com
values written into the source data end pointer (SRC_END_PTR)
and destination data end pointer (DST_END_PTR) are still used
as the addresses for the last transfer as part of the DMA cycle.
However, the start address is computed differently than the address
increment scheme for either source read or destination write.
In the following calculations, N_MINUS_1 is the current count of
transfers to be completed. Additionally, byte swap and address dec-
rement must not be used together for any channel. If used together,
the DMA data transfer operation is unpredictable.
all the combinations of source and destination decrementing and
their data movement direction.
If the source decrement bit is set in the SRCADDR_SET register for
a channel, its source address is calculated as follows:
Source Read Address = SRC_END_PTR + (N_MINUS_1
<< (SRC_INC)) for SRC_INC = 0, 1, 2
or
Source Read Address = SRC_END_PTR for SRC_INC
= 3
If the destination decrement bit is set in the DSTADDR_SET regis-
ter for a channel, its source address is computed as follows:
Destination Write Address = DST_END_PTR +
(N_MINUS_1 << (DST_INC)) for DST_INC = 0, 1,
2
or
Destination Write Address = DST_END_PTR for
DST_INC = 3
Figure 48. Image Decrement
ADuCM356
Figure 48 shows
Rev. A | 168 of 312