Afe Watchdog Timer; Watchdog Timer Features And Block Diagram; Watchdog Timer Operation; Windowed Watchdog Feature - Analog Devices ADuCM356 Reference Manual

Reference Manual

AFE WATCHDOG TIMER

WATCHDOG TIMER FEATURES AND BLOCK
DIAGRAM
To satisfy the IEC 61508 standard requirement for separating the
watchdog timer from all processor clock sources, the analog die
watchdog timer is used to recover from an invalid software state.
After the watchdog timer is enabled by user code, it requires
periodic servicing to prevent it from forcing a reset of the processor.
The required maximum watchdog timer reset period is 16 sec in
gas sensor applications.
The watchdog timer is a windowed timer with an upper and lower
refresh period. The watchdog timer triggers a reset if the following
are true:
The timer is not refreshed before the largest interval. The largest
►
interval is set by the user via the WDTLD register.
The timer is refreshed before the shortest interval. The shortest
►
interval is set by the user via the WDTMINLD register.
The timer is refreshed by writing 0xCCCC to the WDTCLRI
►
register.
A watchdog timer reset is forced by writing a value other than
►
0xCCCC to the WDTCLRI register.
The watchdog timer is clocked by the low frequency oscillator (see
the Clock Divider Configuration Register
all times, except during reset, while in debug mode, and when it is
selectively disabled while in hibernate mode.
The watchdog timer is a 16-bit countdown timer with a programma-
ble prescaler. The prescaler source is selectable and can be scaled
by a factor of 1, 16, 256, or 4096. The analog die watchdog timer
control registers ensure a maximum timeout period of 16383.5 sec
when WDTCON, Bit 8 = 1. WDTCON, Bit 8 = 1 results in the
32.768 kHz clock being divided by 2. When WDTCON, Bit 8 = 0,
the maximum timeout is 8191.75 sec. The default timeout period is
32 sec.

WATCHDOG TIMER OPERATION

After any reset, the watchdog timer is initialized with an initial
configuration. This initial configuration can be modified by user
code. However, setting the watchdog timer enable register write
protects the watchdog timer configuration or enable register so that
the watchdog timer keeps running. Only a reset clears the write pro-
tection and allows reconfiguration of the timer. When the watchdog
timer is not enabled, the watchdog timer can be reconfigured at any
time.
When the watchdog timer decrements to 0, a reset is generated.
This reset can be prevented by writing 0xCCCC to the WDTCLRI
register. Writing 0xCCCC to WDTCLRI causes the watchdog timer
to reload with the watchdog timer configuration in free running
mode. In this case, the watchdog timer immediately begins a new
timeout period and starts to count again.
The reset output of the watchdog timer works solely from the 32
kHz clock and does not require the system clock to be active.
analog.com
section). It is clocked at
Therefore, the reset output can work with all the power-down
modes, including hibernate mode.
In MCU software debugging mode, disable the WDT first before
software debugging. These specific values written to specific regis-
ters eliminate the possibility of rogue code refreshing the watchdog
timer.

WINDOWED WATCHDOG FEATURE

The windowed watchdog feature provides extra robustness to the
watchdog timer for safety critical applications. With the window
feature enabled, the watchdog timer reset fires if user code refresh-
es the watchdog timer either too quickly or too slowly. When the
window feature is enabled (WDTCON, Bit 9 = 1), the watchdog
timer must be refreshed before the counter value reaches 0. The
WDT must also be refreshed after the counter has passed the value
written to the WDTMINLD register.
The following are example instructions to set up the windowed
watchdog feature:
pADI_AFEWDT->WDTLD = 0x800; //16 second time►
out period
pADI_AFEWDT->WDTMINLD = 0x600;
window is 4s after start
pADI_AFEWDT->WDTCON = 0x248;
ble Windowed feature
ADuCM356
// Min
// Ena►
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