Endian Operation; Dma Channel Enable And Disable; Dma Initiator Enable; Power-Down Considerations - Analog Devices ADuCM356 Reference Manual

Reference Manual
DMA CONTROLLER
Aborting DMA Transfers
It is possible to abort a DMA transfer that is in progress by writing
to the bit in the EN_CLR register that corresponds to the channel
that must be aborted. Do not set CFG to 0, because this action can
corrupt the DMA structures.

ENDIAN OPERATION

The DMA controller performs a transfer by default by using a little
endian approach. However, this default behavior can be changed
by setting the corresponding channel bit in the BS_SET register.
The endian operation is referred to as byte swap.
Byte Swap Disabled
Byte swap is disabled by default, in which case, the data transfer
is considered to be little endian. Data arriving from a peripheral
is placed in sequence starting from the LSB of a 32-bit word. For
example, if 16 bytes of data arrive at the SPI as 0x01 (start), 0x02,
0x03, 0x04 ... 0x0F, 0x10, it is stored by the DMA in memory as
follows:
04_03_02_01
08_07_06_05
0C_0B_0A_09
10_0F_0E_0D
Byte Swap Enabled
Byte swap happens on 32-bit data boundaries. The transfer size
must be a multiple of four. Byte swap and address decrement
cannot be used together for any channel. If used together, DMA
data transfer operation is unpredictable. When using byte swap,
ensure that the source data address is constant for the full data
transfer. Byte swap functionality is independent of DMA transfer
size and can be 8-bit, 16-bit, or 32-bit.
If 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04
... 0x0F, 0x10, the data is stored by the DMA in memory as follows:
01_02_03_04
05_06_07_08
09_0A_0B_0C
0D_0E_0F_10

DMA CHANNEL ENABLE AND DISABLE

Before issuing a DMA request, the DMA channel must be ena-
bled. Otherwise, the DMA request for the corresponding channel
is driven as a DMA_DONE interrupt. Any DMA channel can be
enabled by writing to the corresponding bit in the EN_SET register.
The DMA controller disables the channel when the corresponding
DMA_DONE interrupt is generated. However, the user can disable
any channel by writing to the corresponding bit in the EN_CLR
register.
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Whenever a channel is disabled, based on the current state of the
DMA controller, the channel does one of the following:
If the user disables the channel and there is no request pending
►
for that channel, it is disabled immediately.
If the user disables the channel that is not being serviced, but
►
its request is posted, its pending request is cleared, and the
channel is disabled immediately.
If the user disables a channel that has been selected after
►
arbitration but has yet to start transfers, the controller completes
the arbitration cycle and then disables the channel.
If the user disables the channel when it is being serviced, the
►
controller completes the current arbitration cycle.

DMA INITIATOR ENABLE

CFG, Bit 0 acts as a soft reset to the DMA controller. Any activity
in the DMA controller can be performed only when this bit is set
to 1. Clearing this bit to 0 clears all cached descriptors within the
controller and resets the controller.

POWER-DOWN CONSIDERATIONS

Complete all ongoing DMA transfers before powering down the
chip to hibernate mode. However, if the user decides to hibernate
as quickly as possible (current data transfers are ignored), the
DMA controller must be disabled by clearing the CFG, Bit 0 before
entering hibernate mode. If hibernate mode is selected when a
DMA transfer is in progress, the transfer discontinues. The DMA
returns to the disabled state. After hibernate or a POR, the DMA
must be enabled again by setting the CFG, Bit 0.
The following DMA registers are retained in hibernate mode:
PDBPTR
►
ADBPTR
►
RMSK_SET
►
RMSK_CLR
►
PRI_SET
►
PRI_CLR
►
BS_SET
►
BS_CLR
►
SRCADDR_SET
►
SRCADDR_CLR
►
DSTADDR_SET
►
DSTADDR_CLR
►
ADuCM356
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