Clocking Architecture; Clocking Architecture Operation; Required Clock Ratio Between Digital Die And Analog Die System Clocks; Digital Die Clock Features - Analog Devices ADuCM356 Reference Manual

Reference Manual

CLOCKING ARCHITECTURE

CLOCKING ARCHITECTURE OPERATION

The ADuCM356 contains two internal dice. Therefore, there are
two independent clock systems: a digital die clock system and
an analog die clock system. Figure 2
architecture.
REQUIRED CLOCK RATIO BETWEEN DIGITAL
DIE AND ANALOG DIE SYSTEM CLOCKS
To maintain reliable communications between the digital die and
the analog die, the ratio of the digital die system clock frequency
to the analog die system clock frequency must be within the range
of 3:1 and 1:3. For example, if the digital die system clock is set
to 6.5 MHz, the analog die system clock must be >2.2 MHz but
<19 MHz. If this ratio is not maintained, the digital die can lose its
communication link to the analog die.

DIGITAL DIE CLOCK FEATURES

At power-up, the processor executes from the internal 26 MHz
oscillator, with the oscillator output divided by four to give a clock
to the central processing unit (CPU) of 6.5 MHz. User code can
select the clock source for the digital die system clock and can
divide the clock by a factor of 1 to 32, where the clock divider bits
are controlled by Bits[5:0] in the CTL1 register, which allows slower
code execution and reduced power consumption.
When switching clock sources, a stable clock must always be
connected to the core. Otherwise, the system can halt before
connecting to the new clock. The digital die clocks include the
following:
The low frequency oscillator is a 32 kHz internal oscillator.
►
The high frequency oscillator is a 26 MHz internal oscillator.
►
External, 16 MHz and 32 MHz crystal options, routed through the
►
analog die.
External clock input option, routed through the analog die.
►
The root clock is divided into several internal clocks.
►
The reference clock (RCLK) clocks the reference timer in the
►
flash controller. The RCLK controls the time for flash erase and
write operations. By default, RCLK is always connected to a 13
MHz clock source. The clock source is generated by a ½ divider
connected to the 26 MHz high frequency oscillator. Therefore,
the default values of the flash timer registers correspond to a 13
MHz clock.
The high-power buck regulator clocks the high-power buck mod-
►
ule. When the high-power buck regulator is enabled, this clock
source is always 200 kHz. The high-power buck regulator is
enabled and disabled by the CTL1 register in the power manage-
ment unit (PMU).

ANALOG DIE CLOCK FEATURES

At power-up, the internal high frequency oscillator is selected as the
analog front end (AFE) system clock with a 16 MHz setting. User
code can divide the clock by a factor of 1 to 32, where the clock
analog.com
shows the overall clock
divider bits are controlled by CLKCON0, Bits[5:0], which allows
reduced power consumption.
The system performance of the analog die has only been validated
with the system clock = 16 MHz. The analog die clocks include the
following:
AFE low frequency oscillator is a 32 kHz internal oscillator used
►
for the analog die watchdog timer.
AFE high frequency oscillator is a 16 MHz or 32 MHz internal
►
oscillator. The 32 MHz setting is only intended for clocking
the ADC when measuring signals >80 kHz, especially for high
frequency impedance measurements. If the 32 MHz setting is
used, ensure that CLKCON0 Bits[5:0] = 2 to limit the digital die
clock sources to 16 MHz. To select the 32 MHz oscillator option,
use the following sequence:
pADI_AFECON->CLKEN1 |= BITM_AFE►
CON_CLKEN1_ACLKDIS; // Temporarily disable
ACLK
pADI_AFE->HPOSCCON &= (~0x4); // Clear
HPOSCCON[2] = 0 to select 32 MHz output
pADI_AFECON->CLKEN1 &= (~BITM_AFE►
CON_CLKEN1_ACLKDIS); // Re-enable ACLK
The high-power oscillator configuration register is key protected,
and the temporary disabling of the analog clock (ACLK) ensures
a safe switchover of the high frequency oscillator from 16 MHz to
32 MHz or from 32 MHz to 16 MHz.
External 16 MHz and 32 MHz crystal option. If the 32 MHz
►
crystal is used, ensure that CLKCON0, Bits[5:0] = 2 to limit the
digital die clock sources to 16 MHz.
External clock input option. If the 32 MHz crystal is used, ensure
►
that CLKCON0, Bits[5:0] = 2 to limit the digital die clock sources
to 16 MHz.
When using the 32 MHz oscillator on the analog die, the PMBW
►
register in AFECON must be configured for high-power mode.
Note, the ADC clock cannot be divided. It runs at the same
►
speed as the high frequency oscillator selected in CLKSEL,
Bits[3:2].
ADuCM356
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