Analog Devices ADuCM356 Reference Manual page 236

Reference Manual
REGISTER DETAILS: I
Table 303. Bit Descriptions for ASTRETCH_SCL (Continued)
Bits Bit Name Settings
[3:0] MST
0001 to 1110 Automatic initiator clock stretching enabled. The timeout period is defined as follows:
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2
C
15: 8 + DIV 7: 4 − 1
DIV
Description
1 13: 8 − CTL 1 13: 8
UCLK/CTL
2
Note that the I C bus baud rate has no influence on the target stretch timeout period.
1111 Automatic target clock stretching enabled with indefinite timeout period.
Automatic Stretch Mode Control for Initiator. These bits control automatic stretch mode for initiator
operation. These bits allow the initiator to hold the I2C_SCL line low and gain more time to service
an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition
where the initiator indefinitely holds I2C_SCL low. As an initiator transmitter, I2C_SCL is automatically
stretched from the negative edge of I2C_SCL (if the initiator transmit FIFO is empty) before sending an
acknowledge or a no acknowledge for an address byte, or before sending data for a data byte. Stretching
stops when the initiator transmit FIFO is no longer empty or a timeout occurs. As an initiator receiver,
the I2C_SCL clock is automatically stretched from the negative edge of I2C_SCL before sending an
acknowledge or a no acknowledge when the initiator receive FIFO is full. Stretching stops when the
initiator receive FIFO is no longer in an overflow condition or a timeout occurs.
0000 Automatic initiator clock stretching disabled.
15: 8 + DIV 7: 4 − 1
DIV
1 13: 8 − CTL 1 13: 8
UCLK/CTL
1111 Automatic initiator clock stretching enabled with indefinite timeout period.
7: 4
ASTRETCH_SCL
× 2
3: 0
ASTRETCH_SCL
× 2
ADuCM356
Reset Access
0x0 R/W
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