Erasing Flash; Writing Flash; Keyhole Writes; Burst Writes - Analog Devices ADuCM356 Reference Manual

Reference Manual
FLASH CONTROLLER

ERASING FLASH

The flash controller provides page level granularity when erasing
user space through the erase page command. Alternatively, user
code can erase the entirety of user space at once using the mass
erase command. These two commands have the same execution
time.
Write protected pages cannot be erased, and the command is
denied. Pages that are write protected also deny a mass erase
command.

WRITING FLASH

Flash memory operates by settings bits to 1 when erased and
selectively clearing bits to 0 when writing data. No write operation
is capable of setting any bit to 1. For this reason, generalized write
accesses must be prefixed by an erase operation.
Initial uploading of user content generally occurs immediately fol-
lowing a mass erase operation. Subsequent modification of already
written locations in flash generally follows selective page erase
operations with user code. During this process, the user must
copy a full page to SRAM, erase the affected page, modify the
in-memory content, and then finally write the page back to flash.
User space protections may prevent a page erase operation (see
the Protection and Integrity section). All user space protections are
cleared automatically after a mass erase or blank check. Note that
a blank check passes only if all user space is already erased. In
these two cases, there is no user space content to protect.

KEYHOLE WRITES

A keyhole write is an indirect write operation wherein user code
programs memory mapped registers with a target address and
data values, then commands the flash controller to perform a write
operation in the background. The flash controller supports write
access to the flash memory only through keyhole writes. This
constraint on write access enables the flash controller to guarantee
that writes occur properly as atomic data word (64-bit) operations
with an associated ECC byte, if enabled (see the
Integrity section).
If ECC is enabled, multiple writes to a single data word location
cannot be performed without erasing the affected page between
writes. Otherwise, ECC errors are reported. A maximum of two
total writes are permitted to a single flash location (data word)
between erasures regardless of ECC or data values, as per the
flash intellectual property (IP) specifications. Writing any location
Table 221. Status Flags
Flag Name Description
CMDBUSY Command busy. High when the controller is processing a command from the CMD register.
WRCLOSE Keyhole closed. High during the first half of a write command, cleared when keyhole registers are free to be programmed for a subsequent
write command.
CMDCOMP Command complete. Sticky flag, set when a command is completed. Write 1 to clear.
WRALCOMP Write almost completed. Sticky flag, set when approximately 20 μs to 40 μs remains for an ongoing write command. Write 1 to clear.
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more than twice per erasure can damage the nonvolatile memory
or reduce its useful life. If multiple writes per location are required,
disable ECC for some region of flash and target that region for
these write operations.
Keyhole operations consist of writes to the following bits:
KH_ADDR, Bits[18:3]. The target address in flash (for example,
►
0x104). The flash controller automatically trims lower bits to
make the address data word aligned.
KH_DATA0, Bits[31:0]. The bottom 32 bits of the 64-bit data word
►
to be written (for example, 0x76543210).
KH_DATA1, Bits[31:0]. The top 32 bits of the 64-bit data word to
►
be written (for example, 0xFEDCBA98).
CMD, Bits[3:0]. Assert the write command in the flash.
►
After the write command is asserted, the flash controller initiates
a 64-bit dual word write to the address provided in KH_ADDR,
Bits[18:3]. Word (32-bit), half word (16-bit), and byte (8-bit) writes
are not supported. Because only 0 is written to the flash, masking
can be used to write individual bits or bytes as necessary, provided
the user takes the ECC into account.
Do not write to any of the keyhole registers when DMA access is
enabled (UCFG, Bit 0 is set). Writing to these registers manually
while DMA is enabled may result in spurious flash writes and can
put the DMA and flash controllers out of synchronization, potentially
stalling the DMA controller for long periods of time (approximately
20 μs to 40 μs).

BURST WRITES

Each 2 kB page of flash memory consists of eight rows of 256
bytes. Design constraints for programming the flash IP enable back
to back writes within a single row to complete more quickly than
the equivalent writes across row boundaries. For optimizing writes,
attempt to write flash memory in aligned blocks of up to 256 bytes.
For example, Row 0 is from flash offset Address 0x00 to Address
0xFC. Similarly, Row 1023 is from 0x3FF00 to 0x3FFFFC.
To benefit from this write performance gain, the second and subse-
Protection and
quent 64-bit write must be requested before the flash controller
completes the first write. The STAT, Bit 3 flag is set when the first
64-bit write operation is nearing completion. This setting provides
user code with a manageable window of time in which to assert
the next write request. This flag can be polled or an interrupt can
optionally be generated when it is asserted. Further descriptions of
STAT, Bit 3 (WRALCOMP) and other available status flags are in
Table 221.
ADuCM356
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