Target I 2 C Status, Error, And Irq Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: I
Table 292. Bit Descriptions for SCTL (Continued)
Bits Bit Name Settings
0 SLVEN
2
TARGET I C STATUS, ERROR, AND IRQ REGISTER
Address: 0x4000302C, Reset: 0x0001, Name: SSTAT
Table 293. Bit Descriptions for SSTAT
Bits Bit Name Settings
15 Reserved
14 START
13 REPSTART
[12:11] IDMAT
10 STOP
[9:8] GCID
7 GCINT
6 SBUSY
5 NOACK
4 SRXOF
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2
C
Description
supported by the target and is stored in ID0 and ID1, where ID0 contains the first byte of the address and
the upper 5 bits must be programmed to 11110. ID3 and ID4 can be programmed with 7-bit addresses at the
same time.
Target Enable.
0 Target disabled and target state machine flops are held in reset.
1 Target enabled.
Description
Reserved.
Start and Matching Address. This bit is asserted if a start is detected on the I2C_SCL and I2C_SDA
and the device address matches, if a general call code (address = 00000000) is received and general
call is enabled, if a high-speed code (address = 00001XXX) is received, or if a start byte (00000001) is
received. It is cleared on receipt of either a stop or start condition.
Repeated Start and Matching Address. This bit is asserted if a start is already asserted and then a
repeated start is detected. It is cleared when read or on receipt of a stop condition. This bit can drive an
interrupt.
Device ID Matched.
00 Received address matched ID Register 0.
01 Received address matched ID Register 1.
10 Received address matched ID Register 2.
11 Received address matched ID Register 3.
Stop After Start and Matching Address. This bit is set by hardware if the target device receives a stop
condition after a previous start condition and a matching address. Cleared by a read of the status
register. If SCTL, Bit 8 in the target control register is asserted, the target interrupt request asserts when
this bit is set. This bit can drive an interrupt.
General ID. This bit is cleared when SCTL, Bit 4 is set to 1. These status bits are not cleared by a
general call reset.
00 No general call.
01 General call reset and program address.
10 General call program address.
11 General call matching alternative ID.
General Call Interrupt. This bit always drives an interrupt. The bit is asserted if the target device
receives a general call of any type. To clear, write 1 to the GCSBCLR in the target control register. If the
call was a general call reset, all registers are at their default values. If the call was a hardware general
call, the receive FIFO holds the second byte of the general call, which can be compared with the ALT
register.
Target Busy. Set by hardware if the target device receives an I
when the address does not match an ID register, the target device receives an I
repeated start address does not match.
Acknowledge Not Generated by the Target. When asserted, this bit indicates that the target responded
to its device address with a no acknowledge. This bit is asserted if there was no data to transmit and
the sequence was a target read or if the no acknowledge bit was set in the target control register and
the device was addressed. This bit is cleared on a read of the SSTAT register.
Target Receive FIFO Overflow. Asserts when a byte is written to the target receive FIFO and the FIFO
is already full.
ADuCM356
2
C start condition. Cleared by hardware
2
C stop condition, or if a
Reset Access
0x0 R/W
Reset Access
0x0 R
0x0 R
0x0 RC
0x0 R
0x0 RC
0x0 R
0x0 R
0x0 R
0x0 RC
0x0 RC
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