Clocking Status Register; Clock Divider Configuration Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: CLOCK ARCHITECTURE
Table 9. Bit Descriptions for CTL5 (Continued)
Bits Bit Name Settings
3 UCLKI2COFF
2 GPTCLK2OFF
1 GPTCLK1OFF
0 GPTCLK0OFF

CLOCKING STATUS REGISTER

Address: 0x4004C318, Reset: 0x00000000, Name: STAT0
Table 10. Bit Descriptions for STAT0
Bits Bit Name Settings
[15:3] Reserved
2 SPLLUNLK
1 SPLLLK
0 SPLL

CLOCK DIVIDER CONFIGURATION REGISTER

Address: 0x400C0408, Reset: 0x0441, Name: CLKCON0
User must write CLKCON0KEY = 0xA815 before writing to CLKCON0.
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Description
disable this bit to control ACLK out. Before programming the ACLKDIVCNT bits in the CTL1 register,
clear this bit to 0. Otherwise, the ACLKDIVCNT bit is not taken into effect.
0 GPIO clock is enabled.
1 GPIO clock is disabled.
2
I C Clock User Control. This bit disables the I
2
I C UCLK in active and flexi modes. In hibernate mode, the I
effect. This bit is automatically cleared if the user code accesses any of the I
2
0 I C clock is enabled.
2
1 I C clock is disabled.
General-Purpose Timer 2 User Control. This bit disables the General-Purpose Timer 2 clock (muxed
version) and controls the gate in active and flexi modes. In hibernate mode, the General-Purpose
Timer 2 clock is always off and this bit has no effect. This bit is automatically cleared if user code
accesses any of the General-Purpose Timer 2 registers.
0 Timer 2 clock is enabled.
1 Timer 2 clock is disabled.
General-Purpose Timer 1 User Control. This bit disables the General-Purpose Timer 1 clock (muxed
version) and controls the gate in active and flexi modes. In hibernate mode, the General-Purpose
Timer 1 clock is always off and this bit has no effect. This bit is automatically cleared if user code
accesses any of the General-Purpose Timer 1 registers.
0 Timer 1 clock is enabled.
1 Timer 1 clock is disabled.
General-Purpose Timer 0 User Control. This bit disables the General-Purpose Timer 0 clock (muxed
version) and controls the gate in active and flexi modes. In hibernate mode, the General-Purpose
Timer 0 clock is always off and this bit has no effect. This bit is automatically cleared if user code
accesses any of the General-Purpose Timer 0 registers.
0 Timer 0 clock is enabled.
1 Timer 0 clock is disabled.
Description
Reserved. Do not write to this bit.
System Phase-Locked Loop (PLL) Unlock Status. Write a 1 to this bit to clear it.
0 No loss of PLL lock detected.
1 A PLL loss of lock is detected.
System PLL Lock Status. Write a 1 to this bit to clear it.
0 No PLL lock event detected.
1 A PLL lock event is detected.
System PLL Status.
0 PLL is not locked, do not use PLL.
1 PLL is locked and ready for use.
2
C universal clock (UCLK) and controls the gate on the
2
C UCLK is always off and this bit has no
2
C registers.
ADuCM356
Reset Access
0x1 R/W
0x1 R/W
0x1 R/W
0x1 R/W
Reset Access
0 R
R/W1C
0
0 R/W1C
0 R
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