Snapshot 0 Register; Snapshot 1 Register; Snapshot 2 Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER
Table 389. Bit Descriptions for SR2 (Continued)
Bits Bit Name
3 CNTROLLINT
2 Reserved
1 PSINT
0 CNTINT

SNAPSHOT 0 REGISTER

Address: 0x40001430, Reset: 0x0000, Name: SNAP0
SNAP0 is a sticky snapshot of the value of CNT0. It is updated at the same time as its counterparts, SNAP1 and SNAP2, thereby overwriting
any previous values of SNAP1, SNAP0, and SNAP2. This updating and overwriting occurs when the CPU writes a snapshot request key of
0x7627 to GWY.
Table 390. Bit Descriptions for SNAP0
Bits Bit Name Settings
[15:0] VALUE

SNAPSHOT 1 REGISTER

Address: 0x40001434, Reset: 0x0000, Name: SNAP1
SNAP1 is a sticky snapshot of the value of CNT1. It is updated at the same time as its counterparts, SNAP0 and SNAP2, thereby overwriting
any previous value of SNAP1, SNAP0, and SNAP2. This updating and overwriting occurs when the CPU writes a snapshot request key of
0x7627 to the GWY register.
Table 391. Bit Descriptions for SNAP1
Bits Bit Name Settings
[15:0] VALUE

SNAPSHOT 2 REGISTER

Address: 0x40001438, Reset: 0x0000, Name: SNAP2
SNAP2 is a sticky snapshot of the value of CNT2. It is updated as the same time as its counterparts, SNAP0 and SNAP1, thereby overwriting
any previous values of SNAP1, SNAP0, and SNAP2 whenever the CPU writes a snapshot request key of 0x7627 to the GWY register.
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Settings Description
WUT Count Roll Over Interrupt Source. This bit sticks active high when the CNT1 and CNT0
count value rolls over from 2
the WUT to pass through (potentially spanning) these maximum and minimum values.
0 CNT1 and CNT0 have not rolled over since this bit was last cleared.
1 CNT1 and CNT0 have rolled over since this bit was last cleared.
Reserved.
WUT Prescaled Modulo 1 Boundary Interrupt Source. This bit sticks active high whenever
the gated clock that defines the prescaled WUT time unit and the advancement of the WUT
count is activated. For PSINT to cause an interrupt from the RTC, the corresponding enable
bit for the interrupt fan in the PSINTEN bit in CR1 must be active high. This interrupt source
is cleared by writing 1. Full interrupt capability is available for RTC1.
0 The prescaled gated clock for the WUT count in CNT1, CNT0, and CNT2 has not activated
since this bit was last cleared.
1 The prescaled gated clock for the WUT count in CNT1, CNT0, and CNT2 has activated since
this bit was last cleared.
WUT Count Interrupt Source. CNTINT sticks active high whenever the value of CNT1 or CN0
changes. Such an event is not the same as the occurrence of a prescaled WUT time unit (as
denoted by PSINT), because the WUT count can either be redefined or trimmed, which may
or may not lead to value changes. This interrupt source is cleared by writing one to its bit
position in SR2.
0 The value of CNT1 and CNT0 has not changed since this bit was last cleared.
1 The value of CNT1 and CNT0 has changed since this bit was last cleared.
Description
Contains a Sticky Snapshot of CNT0. This channel takes a sticky snapshot of the 47-bit WUT count in
CNT1, CNT0, and CNT2 and stores it in SNAP1, SNAP0, and SNAP2, respectively.
Description
Contains a Sticky Snapshot of CNT1. This channel takes a sticky snapshot of the 47-bit WUT count in
CNT1, CNT0, and CNT2 and stores it in SNAP1, SNAP0, and SNAP2, respectively.
32
− 1 to zero or is trimmed such that the trim increment causes
ADuCM356
Reset Access
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
Reset Access
0x0 R
Reset Access
0x0 R
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