Digital Die Port Mux; Afe Die Digital Port Mux - Analog Devices ADuCM356 Reference Manual

Reference Manual
DIGITAL INPUTS AND OUTPUTS
The following is example code for the GPIO pin interrupt handler
routine:
void GPIO_A_Int_Handler()
{
unsigned int uiIntSta = 0;
uiIntSta = pADI_GPIO1->INT;
if ((uiIntSta & 0x2) ==0x2)
expected on P1.1
{
pADI_GPIO1->INT |= 0x2;
}
}
Table 255. GPIO Multiplex Table
GPIO Pin
GP0 (GP0CON Controls These Bits)
P0.0/SPI0_CLK
P0.1/SPI0_MOSI
P0.2/SPI0_MISO
P0.3/SPI0_CS
P0.4/I2C_SCL
P0.5/I2C_SDA
P0.10/UART_SOUT
P0.11/UART_SIN
GP1 (GP1CON Controls These Bits)
P1.0/SYS_WAKE
BM/P1.1
P1.2/SPI1_CLK
P1.3/SPI1_MOSI
P1.4/SPI1_MISO
P1.5/SPI1_CS
P2.4

AFE DIE DIGITAL PORT MUX

This block provides control over the three digital die GPIO pins.
Two of these pins are bonded out as GPIO0/PWM0 and GPIO1/
Table 256. AFE Die GPIO Mux Table
GPIO 00
GPIO0 Reserved
GPIO1 Reserved
P2.2 (Internal Only) CLK_OUT (GP2CON, Bits[5:4] = 0x0)
analog.com
// interrupt
00
GPIO (GP0CON, Bits[1:0] = 0x0)
GPIO (GP0CON, Bits[3:2] = 0x0)
GPIO (GP0CON, Bits[5:4] = 0x0)
GPIO (GP0CON, Bits[7:6] = 0x0)
GPIO (GP0CON, Bits[9:8] = 0x0)
GPIO (GP0CON, Bits[11:10] = 0x0)
GPIO (GP0CON, Bits[21:20] = 0x0)
GPIO (GP0CON, Bits[23:22] = 0x0)
GPIO (GP1CON, Bits[1:0] = 0x0)
GPIO boot (GP1CON, Bits[3:2] =
0x0)
GPIO (GP1CON, Bits[5:4] = 0x0)
GPIO (GP1CON, Bits[7:6] = 0x0)
GPIO (GP1CON, Bits[9:8] = 0x0)
GPIO (GP1CON, Bits[11:10] = 0x0)
GPIO (GP2CON, Bits[9:8] = 0x0)
Configuration Modes (GP2CON Controls These Bits)
01
PWM0 (GP2CON, Bits[1:0] = 0x1)
PWM1 (GP2CON, Bits[3:2] = 0x1)
Reserved
The following is example code to set P0.3/SPI0_CS as an output.
Write to GP0OUT, GP0SET, GP0CLR, and GP0TGL to set the level
on P0.3/SPI0_CS:
pADI_GPIO0->OEN |= 0x8;
Configure P0.3 as an output

DIGITAL DIE PORT MUX

This block provides control over the GPIO functionality of specified
pins. Some pins have the ability to work as a GPIO or perform other
specific functions. Only configuration of the P2.4 pin of Port 2 is
permitted. Attempted writes to other port pins are not allowed. Any
blank cells in Table 255
Configuration Modes
01
SPI0 serial clock (SCLK) (GP0CON, Bits[1:0] = 0x1)
SPI0 MOSI (GP0CON, Bits[3:2] = 0x1)
SPI0 MISO (GP0CON, Bits[5:4] = 0x1)
SPI0 chip select (GP0CON, Bits[7:6] = 0x1)
I2C I2C_SCL (GP0CON, Bits[9:8] = 0x1)
I2C I2C_SDA (GP0CON, Bits[11:10] = 0x1)
UART SOUT pin (GP0CON, Bits[21:20] = 0x1)
UART SIN pin (GP0CON, Bits[23:22] = 0x1)
GPIO (GP1CON, Bits[3:2] = 0x1)
SPI1 SCLK (GP1CON, Bits[5:4] = 0x1)
SPI1 MOSI (GP1CON, Bits[7:6] = 0x1)
SPI1 MISO (GP1CON, Bits[9:8] = 0x1)
SPI1 chip select (GP1CON, Bits[11:10] = 0x1)
PWM1. The third pin, referred to as P2.2, is an internal pin bonded
to the digital die P0.10/UART_SOUT pin and supports connecting
the AFE die system clock to the digital die.
ADuCM356
are not applicable.
10 11
SPI1 ready (GP0CON,
Bits[7:6] = 0x3)
10
GPIO (GP2CON, Bits[1:0] = 0x2)
GPIO (GP2CON, Bits[3:2] = 0x2)
Reserved
Rev. A | 211 of 312
//
11
Reserved
Reserved
Reserved