Analog Devices ADRV9001 User Manual
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Analog Devices ADRV9001 User Manual

Analog Devices ADRV9001 User Manual

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System Development User Guide for the RF Agile Transceiver Family
ADRV9001 SYSTEM DEVELOPMENT USER GUIDE OVERVIEW
The ADRV9001 is family designator assigned to the System Development User Guide (UG-1828 for new ADRV9002, ADRV9003,
ADRV9004, and upcoming additional family members).
The ADRV9001 System Development User Guide covers:
•
ADRV9002 integrated dual RF transceiver
•
ADRV9003 integrated single RF transceiver (excludes DPD)
•
ADRV9004 integrated dual RF transceiver (excludes DPD)
This user guide provides details on functionality across the entire family. Some family members do not include all the features or
functions. Refer to the individual product data sheet for each product available features and functions.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
ADRV9001 System Development User Guid
Analog Way, Wilmington, MA 01887 U.S.A. • Tel: 781.935.5565 • www.analog.com
Preliminary Technical Data
Rev. PrC | Page 1 of 338
e
UG-1828

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Summary of Contents for Analog Devices ADRV9001

  • Page 1 System Development User Guide for the RF Agile Transceiver Family ADRV9001 SYSTEM DEVELOPMENT USER GUIDE OVERVIEW The ADRV9001 is family designator assigned to the System Development User Guide (UG-1828 for new ADRV9002, ADRV9003, ADRV9004, and upcoming additional family members). The ADRV9001 System Development User Guide covers: •...

  • Page 2: Table Of Contents

    ADRV9001 in Single-Band 2T2R TDD Type Small-Cell Clock Generation ............... 86 Application .................. 14 Multichip Synchronization ............88 ADRV9001 in 1T1R FDD with DPD Type Application ..16 Introduction ................88 ADRV9001 in TETRA Type Portable Radio Application ..18 Theory of Operation ..............88 ADRV9001 in DMR Type Portable Radio Application ..
  • Page 3 Analog Front End (AFE) ............129 ADRV9001 DPD Function ............197 Transmit Data Chain API Programming ......130 ADRV9001 DPD Supported Waveforms ....... 199 Receiver/Observation Receiver Signal Chain ......131 DPD with Frequency Hopping (FH) ........199 Receive Data Chain ..............133 ADRV9001 DPD Performance ..........
  • Page 4 Component Placement and Routing Priorities ....253 TDD Enablement Delays ............321 RF and Data Port Transmission Line Layout ......259 Auxiliary DAC/ADC ..............321 Isolation Techniques Used on the ADRV9001 Evaluation Frequency Hopping TES Examples ........322 Card .................... 266 Radio State ................. 331 Power Supply Recommendations ..........

  • Page 5: How To Use This Document

    Preliminary Technical Data UG-1828 HOW TO USE THIS DOCUMENT START GO TO ADRV9001 TRANSCEIVER OVERVIEW AND LEARN WHAT ADRV9001 IS? ADRV9001 EXAMPLE USE CASES PARAGRAPHS. GO TO ADRV9001 EVALUATION SYSTEM HAVE ADRV9001 PARAGRAPH FOR MORE INFORMATION EVALUATION SYSTEM? HOW TO USE IT.

  • Page 6: Block Diagram

    UG-1828 Preliminary Technical Data BLOCK DIAGRAM RX1A+ DIGITAL SIGNAL PROCESSING: RX1_DCLK_OUT± RX1A– - NARROW/WIDE BAND DECIMATION DATA - DC OFFSET CORRECTION (DC) 0° PORT - QUADRATURE ERROR CORRECTION (QEC) RX1_STROBE_OUT± CMOS-SSI - NUMERICALLY CONTROLLED OSCILLATOR (NCO) 90° - PROGRAMMABLE FIR FILTER (PFIR) RX1B+ LVDS-SSI - AUTOMATIC GAIN CONTROL (AGC)

  • Page 7: Product Highlights

    Preliminary Technical Data UG-1828 PRODUCT HIGHLIGHTS ADRV9002 ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery powered radio equipment and can operate in both frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates from 30 MHz to 6000 MHz covering the VHF, licensed and unlicensed cellular bands, and ISM bands.
  • Page 8 UG-1828 Preliminary Technical Data The LVDS electrical interface supports two modes of operation. The 32 total bits of I and Q data are serialized over one LVDS lane (32 bits composed of 16 bits of I and 16 bits of Q data) or two LVDS-SSI lanes (each dedicated to 16 bits of I or Q data), with two additional lanes total required for a DDR clock and a frame synchronization signal.

  • Page 9: Adrv9003

    Preliminary Technical Data UG-1828 The ADC in the receive chain possesses a high dynamic range. Assuming a mixer gain of 0 dB, the ADC’s noise and maximum input power referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150 dB on a per Hertz basis.

  • Page 10: Adrv9001 Example Use Cases

    With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF to bits signal chains that can serve as the RF front end in small cell type applications. The ADRV9001 dual Rx and Tx signal chains allow the user to implement MIMO or diversity in their system.
  • Page 11 LO Generation In FDD type Small Cell application, ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2x RF LO can be used for uplink and External LO2 operating at 2x RF LO can be used for downlink.

  • Page 12: Adrv9001 In Dual-Band 2Rt2R Fdd Type Small-Cell Application

    RF RECEPTION BAND B (DIVERSITY/MIMO) AND Tx INIT CALIBRATIONS RF TRANSMISSION BAND A AND BAND B (DIVERSITY/MIMO) RF TRANSMISSION BAND A AND BAND B (DIVERSITY/MIMO) Figure 4. ADRV9001 in Dual-Band 2T2R FDD Type Small-Cell Application Rev. PrC | Page 12 of 338...
  • Page 13 RF front end in small cell type applications. Note that in proposed solution, only one band can be used at the time. ADRV9001 dual Rx and Tx signal chains enables user to implement MIMO or diversity in their system. ADRV9001 internal AGC can be used to autonomously monitor and set appropriate gain level for Rx signal chains.

  • Page 14: Adrv9001 In Single-Band 2T2R Tdd Type Small-Cell Application

    With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF-to-bits signal chain that can serve as RF front end in TDD type small cell type applications. ADRV9001 dual Rx and Tx signal chains enables user to implement MIMO or diversity in their system.
  • Page 15 LO Generation In TDD type small cell applications, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. It is also possible to use external LO inputs in this mode of operation. External LO1 operating at 2× RF LO can be used for both uplink and downlink.

  • Page 16: Adrv9001 In 1T1R Fdd With Dpd Type Application

    For systems that demand superior LO phase noise performance, ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for Rx signal chain.
  • Page 17 LO Generation In 1T1R FDD+DPD type applications, ADRV9001 can use its internal LO to generate RF LO1 for uplink and RF LO2 for downlink. For applications with stringent RF LO requirements, the user can use external LO inputs. External LO1 operating at 2×...

  • Page 18: Adrv9001 In Tetra Type Portable Radio Application

    For systems that demand superior LO phase noise performance, ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be used to autonomously monitor and set appropriate gain level for Rx signal chain. For time critical TDD type applications control of the ADRV9001 TRx can be done by toggling control lines.
  • Page 19 The DPD functionality can be used in the 1T1R TDD mode. Maximum channel bandwidth that DPD can support is limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or Rx data can be sent to baseband processor via Rx data port during Tx operation.

  • Page 20: Adrv9001 In Dmr Type Portable Radio Application

    RF front end in DMR type applications. For systems that demand superior LO phase noise performance, ADRV9001 allows user to apply eternal RF LO. ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for the Rx signal chain.
  • Page 21 DGPIOs For DMR type applications, ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to: sent wake up signal to baseband processor, allow baseband processor to move ADRV9001 into Monitor mode using hardware pins (instead API command).

  • Page 22: Adrv9001 In Fdd Type Repeater Application

    RF front end in repeater or frequency translator type applications. ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx can be done thru API commands that use SPI interface.
  • Page 23 RF Front End For LO generation, the ADRV9001 uses internal VCO that generates a square wave type signal. A square wave LO would produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as −50 dBc and 3rd harmonic can be as high as −9 dBc.

  • Page 24: Adrv9001 In A Fdd Type Repeater Application Using Internal Loopbacks

    ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for Rx signal chains. For none time critical FDD type applications control of the ADRV9001 TRx can be done thru API commands that use SPI interface.
  • Page 25 RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO would produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can be as high as −50 dBc and 3rd harmonic can be as high as −9 dBc.

  • Page 26: Adrv9001 In Tdd Type Repeater Application

    Rx signal chains. FPGA or baseband processor is responsible for appropriate time alignment of Rx and Tx time slots. Control of the ADRV9001 Rx and Tx signal chains can be done by toggling control lines. ADRV9001 can provide power amplifier bias voltage by utilizing AuxDAC outputs.
  • Page 27 The DPD functionality can be used in the 2R2T TDD mode. Maximum channel bandwidth that DPD can support is limited by ADRV9001 RF bandwidth divided by 3 or by 5. The DPD operation can be performed by ADRV9001 or ORx data can be sent to baseband processor via Rx data port during Tx operation.

  • Page 28: Adrv9001 In Radar Type Application

    UG-1828 Preliminary Technical Data ADRV9001 IN RADAR TYPE APPLICATION Figure 12. ADRV9001 in Radar Type Application Rev. PrC | Page 28 of 338...
  • Page 29 With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF-to-bits signal chain that can serve as RF front end building block in Radar type applications. ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for Rx signal chains.

  • Page 30: Software System Architecture Description

    SOFTWARE SYSTEM ARCHITECTURE DESCRIPTION This section provides information about the device driver Application Programming Interface (API) software developed by ADI for the ADRV9001 transceivers, as well as outlines the overall architecture, folder structure, and methods for using API software on the customer platform.

  • Page 31: Folder Structure

    ADRV9001 API into a custom folder organization, if required. This operation, however, does not permit the developer the right to modify the content of the ADRV9001 API source code, with the exception of the customer HAL placeholder files, which will be detailed later in this chapter and the SOFTWARE INTEGRATION chapter.

  • Page 32: Customising The System Architecture And File Structure

    /c_src/devices The device folder includes the main API code for the ADRV9001 transceiver as well as auxiliary devices APIs used for the demo of ADRV9001. The /adrv9001 folder contains the high-level function prototypes, data types, macros, and source code used to build the final user software system.
  • Page 33 This function is defined in linux_uio_init.c, found under platforms\linux_uio\. Inspecting this function, the following code snippet is found early in definition: if (NULL != fpga9001) fpga9001->common.devHalInfo = linux_uio_fpga9001_open(); if (NULL != adrv9001) ((adi_adrv9001_hal_linux_uio_Cfg_t *)adrv9001->common.devHalInfo)->fpga9001 = fpga9001; if (NULL == fpga9001->common.devHalInfo) return -1;...
  • Page 34 UG-1828 Preliminary Technical Data Figure 17. API Folder Structure with Customer Interaction Points Highlighted More details are provided on the customer\ folder in the Software Integration chapter, which goes into more specifics on the HAL. At this point in development it is recommended to read the files under the highlighted directories in Figure 17 (primarily the customer\ folder) before proceeding to edit them.

  • Page 35: Software Integration

    UG-1828 SOFTWARE INTEGRATION The ADRV9001 API package was developed using the ZC706 Evaluation platform. This section describes how to use the provided ADRV9001 API in a custom hardware/software environment. This is readily accomplished because the API was developed abiding by C99 constructs while maintaining Linux system call transparency.
  • Page 36 Once done, the adi_platform.c code will automatically switch to using the placeholder customer code under the customer\ folder. Below is provided a code snippet from adi_adrv9001_hal_customer.c, located under customer\adrv9001\. Here can be seen each function that is required by the HAL to support a customer-specific platform. It is advisable to have read the example HAL implementation provided under the linux_uio\ folder to gain an understanding of the purpose of each function, as well as the acceptable return values.
  • Page 37 SPI functionality and the RESET pin control. These are the minimum functions required in order to interact with the ADRV9001 device provided you can power it. In an upcoming section, an example customer HAL file is provided designed to operate the ADRV9001 device using a Raspberry Pi.
  • Page 38 Below we provide some rudimentary examples of how a customer might choose to fill the above listed functions for a Raspberry Pi platform as an example. The Broadcom SPI library for the Raspberry Pi is used to handle all configurations and interactions with the ADRV9001 product.
  • Page 39 Preliminary Technical Data UG-1828 if (!bcm2835_spi_begin()) printf("bcm2835_spi_begin failed. Are you running as root??\n"); return 1; bcm2835_spi_setBitOrder(BCM2835_SPI_BIT_ORDER_MSBFIRST); // The default bcm2835_spi_setDataMode(BCM2835_SPI_MODE0); // The default bcm2835_spi_setClockDivider(BCM2835_SPI_CLOCK_DIVIDER_32768); // 12kHz bcm2835_spi_chipSelect(BCM2835_SPI_CS_NONE); bcm2835_spi_setChipSelectPolarity(BCM2835_SPI_CS0, HIGH); // The default // Set the CE pin to be an output bcm2835_gpio_fsel(CE_PIN, BCM2835_GPIO_FSEL_OUTP);...
  • Page 40 UG-1828 Preliminary Technical Data delay(1); bcm2835_gpio_write(CE_PIN, HIGH); return 0; int32_t customer_adi_adrv9001_hal_resetbPin_set(void *devHalCfg, uint8_t pinLevel) /* Customer code goes here */ if (pinLevel == 1){ bcm2835_gpio_write(RESET_PIN, HIGH); }else{ bcm2835_gpio_write(RESET_PIN, LOW); return 0; In this example of the Raspberry Pi platform the Makefile must also be altered to suit. As this example uses the bcm2835 library, an additional link must be made in the Makefile, as shown here: -lm -lbcm2835 -lpthread This link will allow the compiler to access the bcm2835 library, provided it is installed correctly on the Raspberry Pi.

  • Page 41: Developing The Application

    The developer may need to store other hardware information unique to a particular ADRV9001 device in this structure such as timer instances or log file information. Note for ADRV9001 API there is a requirement that only one thread may control and configure a specific device instance at any given time.
  • Page 42 Modifying these values is not recommended and may impact performance. During this time-out period, the status of ADRV9001 is polled. The frequency of the polling the status during this timeout period may be modified by the user by adjusting the value of the polling interval.

  • Page 43: System Initialization And Shutdown

    TES CONFIGURATION AND INITIALIZATION The TES provides a Config tab that contains all the setup options for the ADRV9001. Under the Config tab, the user could configure each channel of the device for a desired profile under the Device Configuration subtab, which sets high level parameters such as duplex mode, data port sample rates and RF channel bandwidth.

  • Page 44: Api Initialization Sequence

    API functions are discussed briefly in the following subsections. Refer to the doxygen document for details of each API function. Note for MIMO systems with multiple inputs and outputs channels, multiple ADRV9001 devices might be involved. To synchronize among all the devices, it requires a common device clock (DEV_CLOCK) and a multichip synchronization (MCS) signal so that all the internally generated analog and digital clocks are aligned among all the devices.
  • Page 45 Preliminary Technical Data UG-1828 Analog Initialization Analog initialization API adi_adrv9001_InitAnalog() is the very first API call to configure the device after all dependent data structures have been initialized. It mainly sets the master bias, validates the profile settings and configures the analog clocks. Resource Loading After analog initialization, a set of APIs are used to load required resources such as stream image, ARM image, programmable FIR (PFIR) coefficients and so on.

  • Page 46: Shutdown Sequence

    Call adi_adrv9001_Radio_Channel_EnableRf( ) to transition the channel to the RF enabled state. SHUTDOWN SEQUENCE After completing all the operations, call API adi_adrv9001_Shutdown() through TES to safely shut down the ADRV9001 device. It performs a hardware reset to reset the ADRV9001 device into a safe state for shutdown or re-initialization.

  • Page 47: Serial Peripheral Interface (Spi)

    5 pF load @ 75 MHz 0x01 0x01 100 pF load @ 20 MHz Any value that is not listed in the table is invalid. For more details, refer to ADRV9001_API doxygen file provided in ADRV9001 SDK package. Rev. PrC | Page 47 of 338...

  • Page 48: Spi Bus Signals

    UG-1828 Preliminary Technical Data SPI BUS SIGNALS The SPI bus consists of the following signals: • SCLK • • SDIO and SDO SCLK SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low. The minimum SCLK frequency is 1 kHz.
  • Page 49 Preliminary Technical Data UG-1828 Single-Byte Data Transfer When enSpiStreaming = 0, a single-byte data transfer is chosen. In this mode, CSB goes active-low, the SCLK signal activates, and the address is transferred from the baseband processor to the device. In LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by the next 14 bits in order from next LSB to MSB.

  • Page 50: Timing Diagrams

    UG-1828 Preliminary Technical Data • Force the CSB line low and keep it low until the last byte is transferred. • Send the instruction word 0_000 0000 0010 1010 (the first 0 indicates a write operation) to select 0x02A as the starting address. •...

  • Page 51: Spi Test

    • Toggle the resetb pin to reset the ADRV9001 • Write register 0x0 with value 0x3C to set ADRV9001 SPI to 4 wire mode, or with value 0x24 to set ADRV9001 SPI to 3 wire mode • Write whatever value to scratch register 0x009, then read register 0x009 to validate if the read value is the write one Users should use the oscilloscope to probe the SPI bus signal and check if the SPI master follow the timing diagrams in Figure 24 and Figure 25 when above SPI validation can’t pass.

  • Page 52: Data Interface

    One lane data mode, I/Q data or other format data are serialized onto one single lane. • Four lanes data mode, which is valid only when ADRV9001 transmit or receive I/Q samples and I/Q samples are 16 bits wide. In •...
  • Page 53 In LVDS mode, an external 100 Ω differential termination resistor is required for each LVDS pair, and the termination resistors should be located as close as possible to the LVDS receiver. ADRV9001 LVDS in circuit has optional internal 100 Ω termination resistor which can be enabled for LSSI, but ADRV9001 LVDS output circuit does not have internal termination resistors, users should develop appropriate LVDS termination resistors in LVDS receiver.

  • Page 54: Cmos Synchronous Serial Interface (Cmos-Ssi)

    UG-1828 Preliminary Technical Data Table 15. CSSI Electrical Specification Symbol Parameter Units VDIGIO_1P8 Interface power supply voltage 1.71 1.89 Input voltage high VDIGIO_1P8 × 0.65 VDIGIO_1P8 + 0.18 Input voltage low -0.3 VDIGIO_1P8 × 0.35 Output voltage high VDIGIO_1P8 − 0.45 VDIGIO_1P8 Output voltage low 0.45...
  • Page 55 The previous sections described data transfer with I/Q format with 16bit width. When the ADRV9001 internal modulation/demodulation is enabled (refer to the Transmitter Signal Chain and Rx Demodulator sections), the data transfer between ADRV9001 and baseband processor would be 2 bits or 16 bits I only data (denoted as symbol to differentiate with I/Q complex samples). In a symbol format mode, raw data are transferred through this interface using different data size.
  • Page 56 UG-1828 Preliminary Technical Data RX_DCLK_OUT RX_STROBE_OUT RX_DATA_OUT S0_D1 S0_D0 S1_D1 S1_D0 S2_D1 S2_D0 S3_D1 Figure 30. Receive CSSI Timing for 2-Bit Symbols (MSB First) Figure 31 illustrates the transmit CSSI interface (Tx) for 2-bit data symbols. TX_DCLK_OUT TX_DCLK_IN TX_STROBE_IN TX_DATA_IN S0_D1 S0_D0 S1_D1...
  • Page 57 Receive CSSI Interface with 2×, 4×, and 8× Data Clock Rates ADRV9001 receive CSSI supports the 2 times, 4 times, or 8 times of the data clock rate for some applications. Figure 36, Figure 37, and Figure 38 illustrate the receive CSSI interface (Rx1 and Rx2) for 16-bit I/Q data sample with 2×, 4×, and 8×...
  • Page 58 UG-1828 Preliminary Technical Data 16 CYCLES (I SAMPLE) 16 CYCLES (Q SAMPLE) 224 CYCLES (NO SAMPLE) RX_DCLK_OUT RX_STROBE_OUT RX_STROBE_OUT RX_DATA_OUT I0_D15 I0_D14 I0_D0 Q0_D15 Q0_D14 Q0_D0 I1_D15 I0_D14 Figure 38. Receive CSSI timing with 8× Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles Figure 39, Figure 40, and Figure 41 illustrate the Receive CSSI interface (Rx1 and Rx2) in frequency deviation mode with 16-bit data symbol with 2×, 4×, and 8×...
  • Page 59 Preliminary Technical Data UG-1828 RX_DCLK_OUT RX_STROBE_OUT RX_STROBE_OUT I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7 RX_IDATA0_OUT I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15 RX_IDATA1_OUT Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7 RX_QDATA2_OUT RX_QDATA3_OUT Q0_D15 Q0_D14 Q0_D13 Q0_D12 Q0_D11...
  • Page 60 (positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing. When the baseband processor drives out the transmit SSI clock, strobe and data to ADRV9001, the output DDR clock can be in-phase with the strobe/data or delayed quarter cycle of the clock period, it’s up to the user, but the relation between transmit DDR clock and strobe/data must meet the ADRV9001 setup and hold timing specification.

  • Page 61: Lvds Synchronous Serial Interface (Lvds-Ssi)

    Preliminary Technical Data UG-1828 TX_DCLK_OUT TX_DCLK_IN TX_DCLK_IN TX_STROBE_IN TX_STROBE_IN I0_D7 I0_D6 I0_D5 I0_D4 I0_D3 I0_D2 I0_D1 I0_D0 I1_D7 TX_IDATA0_IN I0_D15 I0_D14 I0_D13 I0_D12 I0_D11 I0_D10 I0_D9 I0_D8 I1_D15 TX_IDATA1_IN Q0_D7 Q0_D6 Q0_D5 Q0_D4 Q0_D3 Q0_D2 Q0_D1 Q0_D0 Q1_D7 TX_QDATA2_IN Q0_D15 Q0_D14 Q0_D13 Q0_D12...
  • Page 62 UG-1828 Preliminary Technical Data RX_DCLK_OUT+ RX_DCLK_OUT+ RX_STROBE_OUT+ RX_STROBE_OUT+ I0_D11 I0_D6 I0_D5 I0_D0 I1_D11 I1_D10 RX_IDATA_OUT+/– Q0_D11 Q0_D6 Q0_D5 Q0_D0 Q1_D11 Q1_D10 RX_QDATA_OUT+/– Figure 49. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First) The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high: •...
  • Page 63 Preliminary Technical Data UG-1828 An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock TX_DCLK_OUT (±) for the baseband processor, the user could use TX_DCLK_OUT to generate above LSSI clock, strobe and data signal.

  • Page 64: Enhanced Rx Ssi Mode

    Receive LSSI Interface with 2×, 4×, and 8× Data Clock Rates ADRV9001 receive LSSI supports the 2 times, 4 times, or 8 times of the data clock rate for some applications, which is similar with the Receiver CSSI mode, refer the timing diagrams in Receive CSSI Interface with 2×, 4×, and 8× Data Clock Rates.

  • Page 65: Power Saving For Lssi

    Tx t (Minimum) 550 ps Strobe/data hold after clock HOLD API PROGRAMMING The ADRV9001 SSI configuration is performed in chip initialization stage and based on the following data structure. typedef struct adi_adrv9001_SsiConfig adi_adrv9001_SsiType_e ssiType; Rev. PrC | Page 65 of 338...
  • Page 66 UG-1828 Preliminary Technical Data adi_adrv9001_SsiDataFormat_e ssiDataFormatSel; adi_adrv9001_SsiNumLane_e numLaneSel; adi_adrv9001_SsiStrobeType_e strobeType; uint8_t lsbFirst; uint8_t qFirst; adi_adrv9001_SsiTxRefClockPin_e txRefClockPin; bool lvdsIBitInversion; bool lvdsQBitInversion; bool lvdsStrobeBitInversion; uint8_t lvdsUseLsbIn12bitMode; bool lvdsRxClkInversionEn; bool cmosDdrPosClkEn; bool cmosClkInversionEn; bool DdrEn; bool rxMaskStrobeEn; } adi_adrv9001_SsiConfig_t; In the data structure, the previously mentioned SSI modes are defined for each Tx/RX channel, Table 20 lists the SSI configuration parameters and some default values, users can find the detail data structure and enumerator description in API Doxygen help file.
  • Page 67 Set the enabledness of Rx to Tx SSI interface loopback adi_adrv9001_Ssi_Delay_Configure Programs the SSI delay configuration adi_adrv9001_Ssi_Delay_Inspect Gets the SSI delay configuration from ADRV9001 device adi_adrv9001_Ssi_PowerDown_Set Set the power down mode for the specified channel and SSI type Rev. PrC | Page 67 of 338...

  • Page 68: Cssi/Lssi Testability And Debug

    CSSI/LSSI TESTABILITY AND DEBUG ADRV9001 SSI has built-in test pattern generator and test pattern checker which can help users to quickly test and debug the SSI interface between the ADRV9001 and the baseband processor. Figure 60 illustrates the ADRV9001 SSI testability and debug diagram with a baseband processor.
  • Page 69 The ADRV9001 transmit SSI has a ramp and PRBS (LSSI only) pattern checker, users can configure ADRV9001 TX SSI test mode and transmit ramp or PRBS pattern via SSI to ADRV9001 to verify if SSI works well, or users can also transmit a fixed pattern and configure the ADRV9001 with the specified fixed pattern to verify the SSI work status.

  • Page 70: Microprocessor And System Control

    For this reason, it is necessary to use a stream image for each configuration of the device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also saved automatically. This stream file should then be used when using these configuration files.

  • Page 71: System Control

    Tx2 datapath For ADRV9001 to receive and react to control signals it must be moved to the primed state. The primed state indicates that the system is ready for operation when the transmit and receive channels are enabled by the user. After the channel is primed, in order to start transmit or reception activities, it must be further transitioned from the primed state to the RF_ENABLED state.
  • Page 72 • Enable Setup Delay is the time taken for ADRV9001 to power up its analog front end. This may or may not include PLL tuning time based on the use case, for example, when Tx and Rx share the same IO but at different frequency, PLL tuning is needed at the frame boundary.
  • Page 73 Transmit Timing Definition Transmit timing parameters define the events that take place in order from the start of transmission at the ADRV9001 data port to the end of transmission when the transmit burst is sent through the antenna to the air.
  • Page 74 Figure 63. This could achieve better power savings. For example, if the user measures the propagation delay as 2.5 ms, whereas the enableSetupDelay provided by ADRV9001 is 8 μs, analog front end could be off to avoid burning power for the first 2.492 ms of the propagation time.
  • Page 75 When the frame ends, enableFallToOffDelay could be set in a similar way as discussed in Use Case 1. Note ADRV9001 currently is not controlling the antenna switch, therefore it is the user’s responsibility to switch the antenna on and off at the accurate time.
  • Page 76 The RX_ENABLE pin is controlled by the user to signal ADRV9001 the start and end of a receive burst at the air (Note RX_ENABLE should rise before the start of the receive burst at air to allow powering up analog front end.).
  • Page 77 (Note enableFallToOffDelay is forced to 0 currently by ADRV9001.). This time should be no larger than the guard time before the next frame. The longer this value, the later the next Rx_enable rising edge can occur.
  • Page 78 UG-1828 Preliminary Technical Data rising edge, the minimum guard time is t – t if t is greater than t . In the case of t is less than RxEnaFall2Off TxEnaRise2On RxEnaFall2Off TxEnaRise2On RxEnaFall2Off , TX_ENABLE rising edge could happen t −...
  • Page 79 Timing Parameters with Power Savings Modes ADRV9001 offers several channel power savings modes (Power Saving Mode 0, Power Saving Mode 1, and Power Saving Mode 2) that trade off better power savings with longer transition time to turn on and turn off a transmit or receive channel. Please refer to the Power Saving and Monitor Mode section in this User Guide for more details about power saving modes.
  • Page 80 All above description is for internal LOs scenarios, if ADRV9001 is configured with external LO mode, users take the responsibility to configure or re-tune the external PLLs, ADRV9001 channel power up and power down sequence in different power saving modes are same with Figure 71, users should make sure the external LOs are ready before the enableRiseToAnalogOnDelay is expiry.
  • Page 81 } adi_adrv9001_ChannelEnablementDelays_t Note guardDelay is reserved for future use and forced to 0 by ADRV9001 for both transmit and receive channels. In addition to that, for the transmit channel, holdDelay is also reserved for future use and forced to 0. For the receive channel, fallToOffDelay is also reserved for future use and forced to 0.
  • Page 82 Based on the information provided in Figure 74, user can further configure the ADRV9001 required timing parameters. Default Timing Parameters for Transmit Channels Figure 75 shows the ADRV9001 transmitter required timing parameters and their minimum, maximum, and default values as well as some recommendations are summarized in Table 27.
  • Page 83 Preliminary Technical Data UG-1828 Default Timing Parameters for Receiver Channels Figure 76 shows the ADRV9001 receiver required timing parameters and their minimum, maximum, and default values as well as some recommendations are summarized in Table 28. PIN: RX_ENABLE RxEnaRise2On RX ON: LNA POWER OUT...
  • Page 84 As previously mentioned the enableSetupDelay (EnaSetup) is the time taken for ADRV9001 to power up its analog front end, and ADRV9001 will also take small time to finish the operations to power down its analog front end at the falling edge of the Tx/Rx Enable signals, users should be advised the programable “EnaRise2AnaOn”...
  • Page 85 CH_ENABLE rising edge to DGPIO rising edge is the “enableSetupDelay”. Similarly, if set EnaFall2Off to 0, the time from CH_ENABLE falling edge to DGPIO falling edge will be the time taken for ADRV9001 to fully power down the analog front end.

  • Page 86: Clock Generation

    CLOCK GENERATION In ADRV9001 all clocks for the converters and main digital are generated by CLKGEN. CLKGEN receives from two clocks, a high performance (HP) clock PLL and a low power (LP) PLL. The high performance clock PLL has a programmable frequency range of 7.2 GHz to 8.8 GHz.
  • Page 87 Arbitrary Sample Rate With a programmable frequency range of both HP CLK PLL and LP CLK PLL as mentioned previously, ADRV9001 supports arbitrary sample rate (ASR) mode, which provides user a great flexibility to configure the desired sample rates in their applications. ASR mode supports an almost continuous range of rates up to 61.44 MHz with a list of dead zones mainly due to the limitations in...

  • Page 88: Multichip Synchronization

    ADRV9001 devices. MCS is the solution for this problem to have the data in multiple channels aligned in time. Certain applications not only require the delay to be deterministic but also require phase to be the same. ADRV9001 will also support PLL phase synchronization as one of the operation modes.
  • Page 89 MCS pulses The Figure 83 shows the MCS signal required to be received by ADRV9001. There are a total of 6 pulses. First 4 pulses are for the analog clock divider synchronization, and the last 2 are for the digital clock divider synchronization. Together they will synchronize all internal components of ADRV9001.
  • Page 90 Note if choosing MCSMODE_DIGITAL mode, which does not guarantee phase synchronization, the process is done only once and that’s after CALIBRATED state. This means after all MCS pulses are sent and all ADRV9001 components are synchronized, no more pulse is needed.

  • Page 91: Mcs Substates (Internal Mcs State Transition)

    • Definition: ADRV9001 is in MCS pulse 1-6 transition but not finished. • BBIC or clock chip sends MCS pulses to all ADRV9001 chips synchronously. BBIC monitors MCS status and restart MCS pulses if needed to all ADRV9001 chips. •...

  • Page 92: Sample Delay And Read Delay

    Configure and send MCS pulses BBIC or clock chip will configure MCS with 6 pulses as inputs to ADRV9001 MCS pin. The timing for these pulses is specified as in Table 33. This will be a BBIC specific function implemented by the user. adi_fpga9001_Mcs_Configure() and adi_fpga9001_Mcs_Start() are examples in the SDK provided for the EVB system FPGA board.
  • Page 93 Preliminary Technical Data UG-1828 Figure 87 Rx MCS to Strobe Timing Diagram User needs to calculate them in the following way: Each channel is independent from other channels sampleDelay = MCS_to_Strobe latency – 1 readDelay = 4 Syncing Multiple channels: (ex. TX1 and TX2, or multiple Devices) sampleDelay = Min (all MCS_to_Strobe latency) –...

  • Page 94: Phase Synchronization

    Signal is using CW tones. The reference clock frequency is set to 38.4 MHz. We use LTE61.44 profile for this test. The test is run from 100 MHz to 3GHz with a 100 MHz step, using internal LOs. We also used 5 different ADRV9001 chips for the test.
  • Page 95 Preliminary Technical Data UG-1828 Figure 89 shows the phase error after synchronization of the two LOs, these are internal register reads but should be accurate. Phase between LO1 and LO2 1000 1500 2000 2500 3000 LO Freq [MHz] Chip1 Chip2 Chip3 Chip4 Chip5...

  • Page 96: Synthesizer Configuration And Lo Operation

    SYNTHESIZER CONFIGURATION AND LO OPERATION The ADRV9001 family devices employ four phase-locked loop (PLL) synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump, loop filter, feedback divider, and digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO).

  • Page 97: Auxiliary Synthesizer

    Preliminary Technical Data UG-1828 RFLO1 MUX RFLO2 MUX TX1 MUX TX2 MUX RX1 MUX RX2 MUX Figure 92. LO Switching Network RFLO1 MUX RFLO2 MUX TX1 MUX TX2 MUX RX1 MUX RX2 MUX RX1/ORX1 RX2/ORX2 Figure 93. LO Switching Network (Receiver Channels Configured as Observation Receivers for Transmitter Channels) Note that depending on the application, user has the ability to select best phase noise or best power saving options for better optimization.
  • Page 98 RF PLL Loop Filter Recommendations For optimal phase noise and EVM performance, a lookup table of RF PLL loop filter bandwidth settings is implemented in ADRV9001 firmware. ADRV9001 automatically selects best RF PLL loop filter configuration based on LO frequency. Alternatively, user can program its own RF PLL loop filter bandwidth following instruction outlined in Loop Filter Configuration paragraph.

  • Page 99: Api Operation

    API OPERATION Data Structure and Enums Table 34. Data Structures Related to LO Operation Data Structure Description adi_adrv9001_Device_t Data structure to hold ADRV9001 device instance settings. adi_adrv9001_Carrier_t Carrier structure for carrier configuration. adi_common_Port_e Enumeration of port types. adi_common_ChannelNumber_e Enumeration of channel numbers.
  • Page 100 UG-1828 Preliminary Technical Data API Commands More detailed information including parameters, return values is provided in the doxygen document supplied with SDK package. Table 35. API Commands Related with LO Configuration Settings API Function Description adi_adrv9001_Radio_Channels_EnableRf() Enable or disable RF channel (Transition the specified channel between RF_ENABLED and PRIMED states) (this function only works if channel is in SPI mode) Prime the specified channel (Transition the specified channel between...
  • Page 101 Preliminary Technical Data UG-1828 Note, when changing the LO, user needs to make sure all channels that utilize the LO is configured. For example, if Tx1 and Rx1 are using LO1, and user wants to change LO1, then user needs to configure both Tx1 and Rx1 to achieve that. If all channels (Tx1 Tx2 Rx1 Rx2) are using the same LO, and user needs to change the LO, then user needs to configure all channels (Tx1 Rx2 Rx1 Rx2) to achieve that.

  • Page 102: Frequency Hopping

    This makes very fast frequency hopping possible. Besides ping pong between two LOs, ADRV9001 also support single LO for frequency hopping. This allows LO to be retuned while it’s off air. This way the user can separately hop Rx1/Tx1 and Rx2/Tx2 as well.
  • Page 103 Preliminary Technical Data UG-1828 Figure 100, shows a Tx/Rx frequency hopping using LO muxing. LO muxing is one of the FH modes which will be discussed in later sections. In this diagram we observe Tx/Rx setup signals and sampled at HOP edges, and then indicate the next frame will be Tx or Rx frame respectively.
  • Page 104 UG-1828 Preliminary Technical Data Figure 101, shows a Tx/Rx frequency hopping using LO retune. In contrast, the frame will the information of which channel the frame needs to be at frame n (Tx or Rx), needs to be given at (n-1) frame time. Figure 101 Tx-Rx Frequency Hopping Using LO Retune Hop Signal and Hop Frame Figure 102.

  • Page 105: Modes Of Operation

    Figure 104 Channel Setup Signal for LO Retune The frequency information comes from the BBIC. Before each Tx or Rx setup, ADRV9001 expects to get some message (this may come in various forms which is discussed in later sections) which indicates a frequency. Prior to each hop, the channel (Tx or Rx) information and the frequency information are obtained.

  • Page 106: Channel And Profile Selection

    LO Muxing For short transition times, ADRV9001 requires two LOs to be used in a ping pong operation. This means while one PLL is used for one frame, the other PLL is being retuned for the next frame. During the transition time, the LOs are swapped.

  • Page 107: Frequency Hopping Operation Ranges

    ADRV9001 supports the loading of two tables (table A and table B), each with a minimum length of 1, and a maximum length of 64 entries. (a total of 128 hop entries/frequencies, if two tables are loaded).
  • Page 108 Figure 107, shows an example of automatic increment mode. This example has a 3-entry table. Reading of the entries is done by firmware at the HOP edges. Before first rising edge of HOP signal table should be written into ADRV9001 memory by BBIC, and at the HOP edge the table should be ready to be read by firmware.
  • Page 109 Frequency Hopping Table Real-Time Process If ADRV9001 is configured for real-time process, the frequency will be configured at real time (Hop edge). This, along with the use of two frequency hopping tables, gives user flexibility to load in new frequency hopping tables during frequency hopping operation.
  • Page 110 • At the first rising edge, the ADRV9001 reads the hop table entry from table A (the single entry) and prepares that frequency for the next frame. At this point, the ADRV9001 switches to table B, which currently has no frequency information. Therefore, ADRV9001 will not read from table B yet at his point, it reads from table B at the upcoming HOP edge (the first falling edge).

  • Page 111: Frequency Hopping Calibrations

    User should ensure the Hop Select Pin is set prior to the appropriate channel setup rising edge. • User can use the Hop Select table pin to force the switch to the second table at any time. ADRV9001 does not require the switch to happen after completion on the first table.
  • Page 112 UG-1828 Preliminary Technical Data 3450 3400 <= f < 3500 3550 3500 <= f < 3600 3650 3600 <= f < 3700 3750 3700 <= f < 3800 3850 3800 <= f < 3900 3950 3900 <= f < 4000 4050 4000 <= f <...

  • Page 113: Frequency Hopping Timing

    Preliminary Technical Data UG-1828 FREQUENCY HOPPING TIMING In this section, we will show the timing information for different frequency hopping use cases. It is recommended to also read the Timing Parameters Control in this document because many of the timing parameters are explained there. DWELL DWELL DWELL...
  • Page 114 Delay from ADRV9001 This time is not used for any delays in digital interface to ADRV9001. The user should enable the interface antenna. and begin data transmission enough time prior to the end of the transition time to account for the propagation delay.
  • Page 115 PLL retuning time. propagationDelay Delay from antenna to Rx This parameter will be dynamic profile interface. dependent and board layout dependent. Not necessary to configure ADRV9001, but may be necessary to derive other timing parameters enableRiseToOnDelay Delay between hop edge Min: and the LNA power up.
  • Page 116 Figure 116. TRx Timing For TRx operation, because a hop edge can mark both the start and end of an Rx or Tx frame, the ADRV9001 guarantees that the Rx front end and Tx front end are not powered up at the same time.

  • Page 117: Additional Frequency Hopping Operations

    The delay parameter specifies the delay in terms of hop frames after the first Tx setup rising edge has been received. By design, the ADRV9001 enforces a minimum delay for both Tx and Rx of 1. However, for Tx only, this delay can be greater than 1. If the user sets it to 0, the ADRV9001 defaults the delay to 1.
  • Page 118 UG-1828 Preliminary Technical Data After the first Tx setup rising edge, the user must then continuously send a pulse train of Tx setup signals until the hop edge in which the Tx frame begins on air. After this, the user can maintain any number of consecutive Tx frames, as long as the Tx setup is continuously toggled.
  • Page 119 Preliminary Technical Data UG-1828 For LO retune case, the difference is Tx setup rising edge now marks the beginning of the interface. txAnalogPowerOnFrameDelay starts when hop signal first samples a High of Tx setup signal with value of 3, then decrement to 0 with edge coming hop edge. When reaching 0, Tx analog is powered on.
  • Page 120 ORx Operation ADRV9001 supports ORx operation in frequency hopping mode. ORx in frequency hopping works in the same way as normal TDD mode. During the actual Tx frame, the user can set the ORx enable signal high to enable ORx.

  • Page 121: Diversity Mode

    Primarily, there is increased time required for the ADRV9001 to prepare for an upcoming frame if two channels are enabled. This increased time must be taken into consideration. This time is currently being characterized and more information will be updated in future releases.

  • Page 122: Integration With Other Advanced Features

    UG-1828 Preliminary Technical Data Manual Gain Control In this mode, ADRV9001 will program the manual gain index for each frame based on the gain information in the frequency hopping table (see Frequency hopping table section). ORx Gain Control The ORx gain operates in manual gain control. In this mode, the user should set their desired starting gain index prior to enabling ORx.

  • Page 123: Transmitter Signal Chain

    As mentioned previously, the ADRV9001 supports many NB and WB standards. Depending on the selected standard and the specific symbol rate chosen via the API profile, the interface clock rate can vary significantly. Please note that the CSSI interface is a slow-speed interface and is not able to cover this entire frequency range.

  • Page 124: Datapath

    Then, the DAC output is filtered by the LPF and input to the up-conversion mixer. As shown in Figure 127, the ADRV9001 device also supports another method of FM/FSK modulation named Direct FM/FSK modulation. In this mode, the DUC, IQ FM/FSK, the interpolation stage 2, power amplifier protection and transmitter attenuation blocks (digital part) are all bypassed.
  • Page 125 The transmitter attenuation block controls the transmitter output power. A transmitter gain table with 960 entries is loaded into the ADRV9001’s memory during initialization. (Currently, only the first 840 entries are used and the remaining 120 entries are reserved for future use.) Each entry equals a 0.05 dB gain step.
  • Page 126 UG-1828 Preliminary Technical Data Besides that, another API “adi_adrv9001_Tx_Attenuation_Configure()” is provided to the user to set more configurations for transmitter attenuation block, such as the transmitter attenuation step size. Three transmitter attenuation modes are provided as defined by the enum “adi_adrv9001_TxAttenuationControlMode_e”: typedef enum adi_adrv9001_TxAttenuationControlMode ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BYPASS = 0,...
  • Page 127 Preliminary Technical Data UG-1828 Tx OUTPUT POWER FULL-SCALE OUTPUT POWER DESIRED Tx ATTENUATION CONST_STEP_MODE_STEP_SIZE CONST_STEP_MODE_WAIT_DURATION TX_ATTENUATION<9:0> Figure 130. Constant Step Mode GPIO MODE Another method to control the transmitter attenuation block is through GPIO mode. In this mode, two GPIO pins are used to increment or decrement the current attenuation value.
  • Page 128 Transmitter/Receiver/Observation Receiver Signal Chain Calibrations section. DPD is an optional feature available in the ADRV9001 device to enable users to achieve higher power amplifier efficiency while still meet Error Vector Magnitude (EVM) and adjacent channel leakage ratio (ACLR) requirements in their transmitter signal chain for compliance...

  • Page 129: Analog Front End (Afe)

    Transmitter NCO Internal Signal Source The ADRV9001 has an internal quadrature NCO. It serves 2 major purposes. First, it could be used to generate the calibration tones for the initial calibrations such as the transmitter QEC. Second, users can use this functionality to generate test tones through an API command to disable the data port interface and simplify the design for specific use cases.

  • Page 130: Transmit Data Chain Api Programming

    TRANSMIT DATA CHAIN API PROGRAMMING A set of transmitter data chain APIs are provided for user interaction with the ADRV9001 device transmit datapath. Some of them have been discussed in the previous sections. The following table summarizes the list of API functions currently available with a brief description for each one.

  • Page 131: Receiver/Observation Receiver Signal Chain

    The ADRV9001 supports a RF local oscillator (LO) range from 30 MHz to 6 GHz. RF LOs can be generated via two internal phase lock loops (PLL) or applied externally to the part. The digital subsystem contains an optional digital mixer that is driven by a programmable NCO.
  • Page 132 Therefore, users must ensure an appropriate level of isolation from ADRV9001 transmitter output to the antenna to ensure that test tones are not transmitted by the system. This isolation could be achieved by disabling power amplifier during transmitter init calibration in ELB1.

  • Page 133: Receive Data Chain

    2 is always for Transmitter 2. When users are in control of the observation channel, they will be allowed to configure the ORx based on their requirements such as the ORx gain. When the ADRV9001 device is control of the observation channel, it is responsible to configure the observation channel properly without any user intervention.

  • Page 134: Analog Front-End Components

    The attenuator has 256 gain settings providing an receiver attenuation range from 0 to 20*log(1/256) = -48dB. Typically, only a subset of this range will be used. In ADRV9001, the current range of the attenuation is from 0 to -30dB with a 0.5dB resolution. The gain of the attenuator is calculated by the following equation: Rev.

  • Page 135: Lpf

    As mentioned previously, the ADRV9001 provides a pair of HP ADCs and a pair of LP ADCs to achieve a flexible trade-off between power consumption and linearity performance. The HP ADC is based on Continuous Time Delta Sigma (CTDS) architecture and is 5- bits wide.

  • Page 136: Digital Front End Components

    In ADRV9001, a two-step approach is taken to estimate and correct the DC offset. The first step comprises of an DC estimation step in the digital domain and a correction procedure in the analog domain, which is named as RFDC. The second step is an all-digital DC offset estimation and correction technique that estimates and corrects for any residual DC offset after the first step, which is named as BBDC.

  • Page 137: Qec

    I/Q sinusoid mismatch in both gain and phase, while FDE is mainly caused by the inconsistent filter responses. Because ADRV9001 supports both NB and WB modes, NBQEC and WBQEC algorithms are developed accordingly to handle quadrature error in these 2 modes effectively.

  • Page 138: Receive Data Chain Api Programming

    RECEIVE DATA CHAIN API PROGRAMMING A set of receiver data chain APIs are provided for user interaction with the ADRV9001 device receive datapath. Some of them have been briefly discussed in the previous sections. This set of APIs could be classified into 3 categories: Receiver Gain APIs, Interface Gain APIs and Miscellaneous APIs as shown in Table 48, Table 49 and Table 50, respectively.
  • Page 139 Preliminary Technical Data UG-1828 Rx Miscellaneous API Function Name Description adi_adrv9001_Rx_AdcSwitchEnable_Get Gets the readiness of dynamic switch between Low Power and High Performance ADCs. adi_adrv9001_Rx_AdcSwitch_Configure Configures ADC dynamic switch settings for the specified channel. adi_adrv9001_Rx_AdcSwitch_Inspect Inspects the current ADC dynamic switch settings for the specified channel. adi_adrv9001_Rx_AdcType_Get Gets the current ADC type for the specified channel.

  • Page 140: Transmitter/Receiver/Observation Receiver Signal Chain Calibrations

    As discussed in the Rx Signal Chain section of this User Guide, ADRV9001 includes 2 transmitters and 2 receivers. for each receiver, besides acting as a primary data channel for receiving RF signals, it could also serve as an observation channel, which receives transmit signals through loopback paths.
  • Page 141 For example, during some transmitter initial calibrations, tones are generated and present at transmitter output. Therefore, user should ensure appropriate level of isolation from ADRV9001 transmitter output to antenna to make sure that test tones are not transmitted by the system. This isolation could be achieved by disabling power amplifier during transmitter initial calibration.
  • Page 142 UG-1828 Preliminary Technical Data ADI_ADRV9001_INIT_CAL_RX_ALL = 0x001FFE00, ADI_ADRV9001_INIT_CAL_RX_TX_ALL = 0x001FFFFF, ADI_ADRV9001_INIT_CAL_SYSTEM_ALL = 0x00C00000, } adi_adrv9001_InitCalibrations_e The following enumerator type defines the operating modes for initial calibrations: typedef enum adi_adrv9001_InitCalMode ADI_ADRV9001_INIT_CAL_MODE_ALL, ADI_ADRV9001_INIT_CAL_MODE_SYSTEM_AND_RX, ADI_ADRV9001_INIT_CAL_MODE_LOOPBACK_AND_TX, ADI_ADRV9001_INIT_CAL_MODE_ELB_ONLY }adi_adrv9001_InitCalMode_e; in which ADI_ADRV9001_INIT_CAL_MODE_ALL is for running all the selected initial calibrations, including both receiver (non- loopback and loopback paths) and transmitter initial calibrations.
  • Page 143 Preliminary Technical Data UG-1828 Bits Corresponding Enum Calibration Description the same for all dynamic datapath profiles, gain indices and frequency regions and so on The calibration need only be performed on a single channel. ADI_ADRV9001_INIT_CAL_TX_DAC Tx DAC Initial This is used to calibrate the DAC for the required profile Calibration bandwidth.
  • Page 144 In all the diagrams, grayed-out lines and blocks are not active in the calibration. It should be noted that as the ADRV9001 ARM performs each of the calibrations, it is tasked with configuring the ADRV9001 device as per the diagrams below, with respect to enabling/disabling paths, and so on No user input is required in this regard.
  • Page 145 50 Ω. Transmitter Initial Calibrations Utilizing Internal Signal Generation and ILB Figure 140 shows a high level block diagram of system configurations for transmitter initial calibrations utilizing internal signal generation and ILB path. ADRV9001 HP ADC LP ADC 0°...
  • Page 146 QEC and LO_LEAKAGE correction values are applied to the transmitter channel by the ADRV9001 ARM. TX_DCC estimates the duty cycle error in the digital domain but applies the correction in the analog domain. TX_ATTEN_DELAY measures the delay between the transmitter digital attenuation block and transmitter analog attenuation block and it uses the ILB for delay observation and estimation.
  • Page 147 In all the diagrams, grayed-out lines and blocks are not active in the calibration. Blue blocks are related calibrations. It should be noted that the ADRV9001 ARM performs each of the calibrations. It is tasked with configuring the ADRV9001 device as per the diagrams below, with respect to enabling/disabling paths, and so on.
  • Page 148 UG-1828 Preliminary Technical Data prevents the calibrations tones from reaching antenna through RF coupling. 50Ω termination is needed to prevent tone signals bouncing back from external LNA output and reaching receiver input confusing internal calibrations. Configure the Initial Calibrations Through TES To achieve optimal performance, all initial calibrations should be enabled.
  • Page 149 Preliminary Technical Data UG-1828 Table 54. Initial Calibration Comparison Summary Re-Run after Signal Used LO Change >100 MHz or Calibration User Run After ÷2 (Tones, External Override Run at Boundary Wide-band, Termination Dependent on Which Bits Enum Capability Boot Change None) Needed Init Cals to be Run First...

  • Page 150: Tracking Calibrations

    UG-1828 Preliminary Technical Data Re-Run after Signal Used LO Change >100 MHz or Calibration External User Run After ÷2 (Tones, Override Run at Boundary Wide-band, Termination Dependent on Which Bits Enum Capability Boot Change None) Needed Init Cals to be Run First Not enabled Not enabled Not enabled...
  • Page 151 UG-1828 Tracking Calibrations API Programming The ADRV9001 ARM in the device is tasked with scheduling/performing tracking calibrations to optimize the performance of the device during its operation. Tracking calibrations are performed using the top-level API function adi_adrv9001_cals_Tracking_Set( ). The tracking calibrations performed is based on the tracking calibration configuration defined by the following data structure: typedef struct adi_adrv9001_TrackingCals adi_adrv9001_TrackingCalibrations_e chanTrackingCalMask[ADI_ADRV9001_MAX_RX_ONLY];...
  • Page 152 UG-1828 Preliminary Technical Data Bits Corresponding Enum Calibration Description ADI_ADRV9001_TRACKING_CAL_TX_LO_LEAKAGE Tx LOL This performs tracking LOL calibration. It estimates the Tracking LOL on-the-fly and applies the cancellation in the digital Calibration domain. It uses the Tx path and an loopback path (external loopback path preferred if available).
  • Page 153 Preliminary Technical Data UG-1828 Bits Corresponding Enum Calibration Description ADI_ADRV9001_TRACKING_CAL_RX_RSSI Rx RSSI This is used to enable/disable Rx signal strength Tracking measurement on-the-fly. Calibration External System Requirements for Tracking Calibrations Different from initial calibrations, tracking calibrations are performed on-the-fly with real-time traffic data. Therefore, it is mostly transparent to the users and fully controlled by the internal micro-processor.

  • Page 154: Receiver Gain Control

    RECEIVER GAIN CONTROL The ADRV9001 receivers feature automatic and manual gain control modes for flexible gain control in a wide array of applications. It controls the gain at various stages of the receiver datapath to avoid overloading during the onset of a strong interferer. In addition, it could ensure that the receiver digital output data is representative of the RMS power of the receiver input signal so that any internal front-end gain changes to avoid overloading are transparent to the baseband processor.

  • Page 155: Receiver Datapath

    Figure 148 shows the simplified receiver datapath and gain control blocks. The receivers have front end attenuators prior to the mixer stage that are used to attenuate the signal in the analog domain to ensure the signal does not overload the receiver chain. Note ADRV9001 provides about 20dB gain so the front end gain attenuator further attenuates signal from that level.
  • Page 156 UG-1828 Preliminary Technical Data EXTERNAL FRONT END GAIN ATTENUATOR WB/NB DECIMATION HB FILTERING (DECIMATION GAIN GAIN (DECIMATION STAGE 2) STAGE 1) INTERFACE DIGITAL GAIN GAIN CONTROL (SLICER) ANALOG PEAK HB PEAK POWER RSSI DETECTOR DETECTOR DETECTOR GAIN CONTROL BLOCK (AGC, MGC) DGPIO(S) Figure 148.
  • Page 157 The gain table maintains a gain step of 0.5 dB between adjacent gain indices and it assumes that the LNA step sizes are accurate. The new Rx gain table is created by first assuming the max LNA Gain (0dB) until the ADRV9001 front-end attenuator “runs out of ”...

  • Page 158: Gain Control Modes

    UG-1828 Preliminary Technical Data The above example uses Rx gain correction table. The similar algorithm applies to generate the new Rx gain compensation table with only one difference: the digital gain should also compensate the LNA attenuation besides the front end attenuation therefore based on the External Gain control word setting, the digital gain needs to be further adjusted.
  • Page 159 Preliminary Technical Data UG-1828 • Peak/Power Detect mode, where information from both the power detector and the peak detectors are used jointly to make gain changes. Peak Detect Mode In this mode, the peak detectors alone are used to inform the AGC to make gain changes. This section explains the basic premise of the operation, while more explicit details of configuring the peak detectors is covered in subsequent sections.
  • Page 160 UG-1828 Preliminary Technical Data INTERFERER PRESENT GAIN DECREMENT (apdGainStepAttack/ hbGainStepAttack) GAIN DECREMENT (apdGainStepAttack/ apdHighThresh/ hbGainStepAttack) hbHighTresh SIGNAL LEVEL GAIN INCREMENT (apdGainStepRecovery/ hbGainStepHighRecovery) apdLowThresh/ hbUnderRangeHighTresh GAIN INCREMENT (apdGainStepRecovery/ GAIN UPDATE hbGainStepHighRecovery) PERIOD INTERFERER REMOVED Figure 150. APD/HB Thresholds and Gain Changes Associated with Underrange and Overrange Conditions It is possible to enable a fast attack mode whereby the AGC is instructed to reduce gain immediately when an over range condition occurs, instead of waiting until the next expiry of the gain update counter using changeGainIfThreshHigh.
  • Page 161 Preliminary Technical Data UG-1828 a multiple of agcUnderRangeLowInterval. Finally, when the signal level is increased above hbUnderRangeMidThresh, the gain is incremented by hbGainStepHighRecovery following the expiry of agcUnderRangeHighInterval, which is a multiple of agcUnderRangeMidInterval. The multiple thresholds and interval parameters allow for faster gain recovery. Typically, agcUnderRangeHighInterval could be set to gain update counter as shown in Figure 152.
  • Page 162 UG-1828 Preliminary Technical Data The apdLowThresh has priority in terms of preventing recovery. If apdLowThresh reports an over range condition (sufficient signal peaks have exceeded its threshold in a gain update counter period), then no further recovery is allowed. apdLowThresh and hbUnderRangeHighThresh should be configured to be as close to the same value of dBFS, but assuming some small difference between the thresholds, then as soon as apdLowThresh is exceeded, recovery will no longer occur.
  • Page 163 Preliminary Technical Data UG-1828 The power detect provides the RMS power measurement of the receiver data at the output of HB Filtering block. In power detect mode, the AGC compares the measured signal level to programmable thresholds which provide a 2nd order control loop, whereby gain can be changed by larger amounts when the signal level is farther from the target level while make smaller gain changes when the signal is closer to the target level.
  • Page 164 UG-1828 Preliminary Technical Data Peak Detect and Peak/Power Detect Mode Comparison Among the two detect modes, peak detect offers the quickest response time to overload signals by employing “fast attack” mode. It allows the AGC to respond within hundreds of nanoseconds in overload scenarios. In addition, the peak detect also provides “fast recovery” option to increase the gain of the desired signal quickly when an interferer disappears.
  • Page 165 Preliminary Technical Data UG-1828 properly, which can be done through API command. The feedback information can be configured into 2 modes, the peak detect mode and peak and power detect mode. In peak detect mode, the over-range and under-range conditions of both APD and HB detectors will be provided through DGPIO pins to user.

  • Page 166: Gain Control Detectors

    UG-1828 Preliminary Technical Data GAIN CONTROL DETECTORS In this section, three gain control detectors will be discussed in more details. Analog Peak Detector (APD) The analog peak detector is located in the analog domain following the TIA filter and prior to the ADC input. It functions by comparing the signal level to programmable thresholds.
  • Page 167 Preliminary Technical Data UG-1828 Table 67. APD Attack and Recovery Step Sizes Gain Change Step Size Gain Attack apdGainStepAttack Gain Recovery apdGainStepRecovery Step size refers to the number of indices of the gain table the gain is changed. As explained earlier, the gain table is programmed with the largest gain in the Max Gain Index (typically index 255), with ever decreasing gain for decreasing gain index.
  • Page 168 UG-1828 Preliminary Technical Data The HB detector has a number of programmable thresholds. Some of these thresholds are only used in the fast recovery mode of the peak detect AGC configuration, as summarized in Table 68. Table 68. HB Overload Thresholds HB Threshold Usage hbHighThresh...

  • Page 169: Agc Clock And Gain Block Timing

    AGC CLOCK AND GAIN BLOCK TIMING The AGC clock is the clock which drives the AGC state machine. In ADRV9001 device, the default AGC clock (to support a set of standard sample rates) is at 184.32 MHz. When arbitrary sample rate is adopted in Rx, the AGC clock could vary.

  • Page 170: Analog Gain Control Api Programming

    UG-1828 Preliminary Technical Data IMMEDIATE GAIN ATTACK GAIN ATTACK TYPE 2 SLOW 5 AGC SLOW SLOW 5 AGC LOOP LOOP LOOP CLOCK CLOCK GAIN UPDATE COUNTER GAIN UPDATE COUNTER SETTLING SETTLING SETTLING CYCLE CYCLE DELAY DELAY DELAY DELAYED DELAYED GAIN GAIN RECOVERY RECOVERY...
  • Page 171 Preliminary Technical Data UG-1828 Figure 160 describes a high level flow chart of Rx gain control programming. Note the final step is to configure any GPIOs as necessary such as GPIO inputs which allow the AGC gain update counter to be synchronized to a slot boundary, or DGPIOs to directly control the gain index.
  • Page 172 UG-1828 Preliminary Technical Data Table 71. adi_adrv9001_GainControlCfg_t Structure Definition Default Parameter Description Min Value Value Value peakWaitTime Number of gain control clock cycles to wait before enabling peak detectors after a gain change. maxGainIndex Maximum gain index allowed. Must be greater than minGainIndex and be a valid gain index.
  • Page 173 Preliminary Technical Data UG-1828 Table 72. adi_adrv9001_PowerDetector_t Structure Definition Default Parameter Description Value Value Value powerEnableMeasurement 1: Power Measurement block enabled. 0: Power Measurement block disabled. underRangeHighPowerThresh Threshold (negative sign assumed) which defines the lower boundary on the stable region of the power detect gain control mode.
  • Page 174 UG-1828 Preliminary Technical Data Default Parameter Description Value Value Value feedback_apd_high_apd_low A pair of DGPIO pins to retrieve the apd detector low threshold counter exceeded status and apd high threshold counter (not (Select (not exceeded status assigned) DGPIO assigned) pins 14 and 15) Table 73.
  • Page 175 Preliminary Technical Data UG-1828 Default Value Parameter Description Min Value Value (TBD) apdGainStepRecovery The number of indices that the gain index pointer should be increased in the event of an APD Under range event occurring in Peak Detect AGC mode. The step size in dB depends on the gain step resolution of the gain table (default 0.5dB per index step).
  • Page 176 UG-1828 Preliminary Technical Data Default Value Parameter Description Min Value Value (TBD) hbGainStepLowRecovery Only applicable in fast recovery mode of peak detect AGC. This sets the number of indices that the gain index pointer should be increased in the event of an HB Under Range Low Threshold Under Range Event.

  • Page 177: Digital Gain Control And Interface Gain (Slicer)

    UG-1828 A set of receiver gain control APIs are provided for user interaction with the ADRV9001 device. Some of them have been mentioned in the previous sections. The following table summarizes the list of API functions currently available with a brief description for each one.
  • Page 178 UG-1828 Preliminary Technical Data gain is not required. In the second mode, it passes the full 22-bit I/Q data from the receiver data path to the interface without rounding. Therefore, it lowers the quantization noise without the need for additional interface gain. It uses 32 bit I data and 32 bit Q data on the interface for CMOS 1-lane (64-bit) and LVDS 2-lane (32-bit I data and 32-bit Q data).

  • Page 179: Digital Gain Control And Interface Gain Api Programming

    Preliminary Technical Data UG-1828 Input Power Level 1 Input Power Level 2 Input Power Level 3 Figure 163. Bit Width of Input Signal with Increasing Power Levels The slicer is used to attenuate the data such that it can fit into the resolution of the data port. Since the output is a shifted version of the input, the slicer can only handle gains that are in ±6 dB steps.

  • Page 180: Usage Recommendations

    UG-1828 Preliminary Technical Data adi_adrv9001_RxGainTableType_e gainTableType; /* 0: Gain Correction table 1: Gain Compensation table adi_adrv9001_RxInterfaceGain_e gain; /* a value between 0 and 9 (0x0 = 18dB, 0x1 = 12dB, 0x2 = 6dB, 0x3 = 0dB, 0x4 = -6dB, 0x5 = -12dB, 0x6 = -18dB, 0x7 = -24dB, 0x8 = -30dB, 0x9 = -36dB).

  • Page 181: Tes Configuration And Debug Information

    Gain Control Mode is selected as Automatic. When the Gain Control Mode is selected as Manual Pin or Manual SPI, it further enables the ADRV9001 internal signal detectors in either Peak Only or Peak and Power mode. By configuring the GPIO pins, user is allowed to retrieve the signal detector status which could be used to control receiver gain in Manual mode.
  • Page 182 UG-1828 Preliminary Technical Data Figure 166. TES Configuration for Rx Interface Gain, Signal Detection Parameters and Manual Control Mode Parameters (when AGC is Configured) Rev. PrC | Page 182 of 338...
  • Page 183 Preliminary Technical Data UG-1828 Figure 167. TES Configuration for Rx Interface Gain, Signal Detection Parameters and Manual Control Mode Parameters (when MGC Pin is Configured) After finishing all the configurations, user could start the receive operations and observe the receiver gain changes. It is recommended to start from the default settings and change the parameters one by one as needed.

  • Page 184: Rx Demodulator

    Rx NARROW-BAND DEMODULATOR SUBSYSTEM ADRV9001 Rx narrow-band demodulator subsystem, denoted by rxnbdem, is the digital baseband backend partition of ADRV9001 Rx channel. Note that narrow band, commonly for a wireless communication system, if the channel spacing, also known as channel bandwidth, is no more than 1 MHz, we call it “Narrowband System”.
  • Page 185 Preliminary Technical Data UG-1828 In a communication system, a desired signal is transmitted by the transmitter at RF over the air. Since the clock reference at the transmitter and the receiver are independent, this may result in the RF carrier frequency offset between the transmitter and the receiver. This frequency difference is named by the carrier frequency offset (CFO).
  • Page 186 UG-1828 Preliminary Technical Data The Rx programmable FIR can be loaded a customized lowpass filter profile to stop the adjacent channel interference, which is helpful to achieve better channel selectivity. For example: as shown in Figure 171, before the CFO is corrected, the BBIC may program a loose filter profile onto the Rx Programmable FIR to perform common filtering.
  • Page 187 Note: The resampler configuration is not supported by current ADRV9001 software release yet. Round Module Round in rxnbdem is to map the ADRV9001 internal datapath bit-width to the Rx SSI output. This module can be bypassed if users choose IQ-22bit mode.

  • Page 188: Normal Iq Output Mode

    The Normal IQ Output mode is applicable for both wideband and narrow band as the frequency discriminator bypassed. Except the Rounding, all other modules can be bypassed. See Figure 175 ADRV9001 Rx narrow-band demodulator can be the common output stage of Rx channel.

  • Page 189: Api Programming

    PFIR pointers are NULL. The ADRV9001 performs the PFIR coefficients switch for all channels that have new coefficients prepared and waiting when the API command adi_adrv9001_arm_Profile_Switch() is called. If ADRV9001 is in PRIMED state, the new coefficients will take effect on the next transition to RF_ENABLED.
  • Page 190 # PFIR_GAIN_0DB for i in range(pfir_dmr_12p5k.numCoeff): pfir_dmr_12p5k.coefficients[i] = pfir_dmr_12p5k_coeff[i] Adrv9001.arm.NextPfir_Set(1, pfir_fm_12p5k) # put in the right filter object Adrv9001.arm.Profile_Switch() NB Programmable FIR API Programming Same with Rx PFIR, a profile predefined set of NB PFIR coefficients (customized NB PFIR coefficients will be supported in the later software release) are automatically loaded during chip initialization, there is no need for baseband processor to call any PFIR coefficients loading API function.

  • Page 191: Power Saving And Monitor Mode

    ADRV9001 software adds additionally static and dynamic power saving schemes in order to extend the power saving feature to a broader market beyond DMR. ADRV9001 defines five extra power down modes that provides from low to high power saving but short to long recovery time, details will be introduced in the following section.

  • Page 192: Power-Down/Power-Up Channel In Calibrated State

    User should notice that these two APIs can only be called in Calibrated state. Figure 177 shows a DMR radio switch from TX only frames into TX/RX alternate frames, ADRV9001 is initialized with Tx and Rx enabled, at the beginning of TX only frames, baseband processor can bring the RX channel into Calibrated State and power it down.
  • Page 193 Preliminary Technical Data UG-1828 Figure 178 shows TX/RX Enable pin powers up/down channels. If Tx/Rx Enable Pin power down mode is set to mode 1, TX1/RX1 Enable falling edge powers down TX1/RX1 PLL and TX1/RX1 datapath, rising edge powers them up. As mentioned previously, the higher power down mode, the longer recovery time, users should make sure their system has enough transition time between the power down and power up of the same component if users set a high power down mode.

  • Page 194: Monitor Mode

    TX enable falling edge. Another option is user can power down more by using System Power Saving if the dark gray area is very long. User can set power down mode 3 to 5 to power down most of ADRV9001 components to save power and wake them up by DGPIO falling edge early enough before TX enable rising edge.
  • Page 195 Monitor modes support there type of system power down modes which are same with the System Power Saving mode. The initial, sleep and detection durations are user configurable, and users can decide detection first or sleep first when ADRV9001 is moved into monitor mode.
  • Page 196 ADRV9001 has the option to buffer the latest incoming data in Monitor Mode “Detecting" cycle, once a valid incoming signal is detected and the baseband processor has been waked up by ADRV9001, ADRV9001 can send out the buffered Rx data to baseband processor. This procedure can make sure the baseband processor won’t miss the valid incoming signal when it’s in the sleep state.

  • Page 197: Digital Predistortion

    Figure 182. Ideal Power Amplifier Output vs. Actual Power Amplifier Output ADRV9001 DPD FUNCTION The ADRV9001 device provides a fully integrated DPD function that supports both narrow-band (NB) and wide-band (WB) applications. It is a hardware/software combined solution which performs linearization of the PA by pre-distorting the digital transmit signal with the inverse of the PA’s nonlinear characteristics.
  • Page 198 Figure 183. High Level Block Diagram of DPD Algorithm In the ADRV9001 device, DPD is considered as one of the transmitter tracking calibrations. It is a real-time signal processing with iterative updates to account for hardware variations such as temperature and power level changes. Similar to some other transmitter tracking calibrations, it requires a loopback path from the transmitter to the observation receiver (ORx) to perform the calibration.

  • Page 199: Adrv9001 Dpd Supported Waveforms

    Multicarrier In theory, DPD can support any profile with a RF signal bandwidth less than 1/5 of the ADRV9001 system frequency. For example, if the ADRV9001 has a system frequency of 184.32MHz, DPD can support a signal bandwidth if it is less than 36.864MHz.
  • Page 200 UG-1828 Preliminary Technical Data 18000 16000 14000 12000 10000 8000 –10 6000 –20 4000 –30 2000 –40 –50 2000 4000 6000 8000 10000 12000 14000 16000 18000 INPUT AMPLITUDE (Linear) INPUT AMPLITUDE (Linear) ×10 Figure 185. Raw Transmit Signal Input vs. Nonlinearized Power Amplifier Output 18000 16000 14000...

  • Page 201: Closed Loop Gain Control (Clgc)

    PA. Therefore, it is crucial to always enable CLGC while DPD is active. As the first step of CLGC, user should set up a target transmit gain. This could be measured through ADRV9001 by using the “CLGC Loop Open” method. The detailed steps of measuring target gain will be discussed later. After the measurement, ADRV9001 provides user both an unfiltered and a filtered transmit gain value.
  • Page 202 , the subscripted t represents the index for the tap, l represents the amplitude delay, and i represents the order of the power term. t l i ADRV9001 only supports 0th to 7th order power term in the function ψ (|d(n – l )|).
  • Page 203 Preliminary Technical Data UG-1828 Parameter Type Description Default Note changeModelTapOrders bool Sets “TRUE” to use the model tap orders defined by FALSE The default model tap “modelOrdersForEachTap”. Set “FALSE” to ignore order for DPD Model 4 is: “modelOrdersForEachTap” and use the default order. [0] = 0x001F, [1] = 0x007F, [2] = 0x001F,...
  • Page 204 UG-1828 Preliminary Technical Data Figure 189. TES Configuration for Enabling DPD/CLGC Tracking Calibration For DPD/CLGC to work, the profile must indicate that there exists an external loopback connection and an external PA for this channel. This can be done by setting “Board Configurations” in TES properly, as shown in Figure 190. Figure 190.
  • Page 205 – 1 – 2 Figure 191. ADRV9001 DPD Model 4 LUT Configuration As shown in Figure 191, d(t) is the raw complex transmit signal before predistortion. Its amplitude is the basis that the DPD actuator uses to predistort the d(t) via its L UT. The LUT consists of four taps, which are calculated with precomputed DPD coefficients α, as the...
  • Page 206 UG-1828 Preliminary Technical Data represent | ���� ( ���� − ���� )| ) B[0] = 0x07, B[1] = 0x7F, B[2] = 0x07 and B[3] = 0x06. (Note Tap 0 and Tap 2 should always be the same. For simplicity GUI uses X to ����...
  • Page 207 Preliminary Technical Data UG-1828 uint32_t dpdSamplingRate_Hz; uint8_t clgcLoopOpen; int32_t clgcGainTarget_HundredthdB; uint32_t clgcFilterAlpha; int32_t clgcLastGain_HundredthdB; int32_t clgcFilteredGain_HundredthdB; } adi_adrv9001_DpdCfg_t Table 84 briefly summarizes all the DPD/CLGC post initial calibration parameters described in the data structure. Table 84. DPD/CLGC Post Initial Calibration Parameters Parameter Type Description...
  • Page 208 UG-1828 Preliminary Technical Data Parameter Type Description Default Note switching, but could hurt convergence. A coefficient of zero means no filtering. dpdSamplingRate_Hz uint32_t Sampling rate in Hz for the Read only. No DPD actuator and capture. effect on DPD configuration. clgcLoopOpen uint8_t Open or close the gain loop.
  • Page 209 This parameter should be configured by user to notify ADRV9001 about the gain target for CLGC in an accuracy of hundredth of a dB. clgcFilterAlpha This parameter stands for the coefficient of a single pole filter to smooth the gain measurement. The min value is 0 which is equivalent to disable this filter by using the instantaneous gain measurement result.

  • Page 210: Board Configuration

    ADRV9001 transmit output to ORx input. User should measure this delay and provide it to ADRV9001 before initial calibration. The measured delay is then used to compensate the delay between x(t) and y(t). This parameter is critical especially for WB applications due to high sample rate.

  • Page 211: Save And Load Dpd Coefficients From Last Transmission

    SAVE AND LOAD DPD COEFFICIENTS FROM LAST TRANSMISSION The ADRV9001 DPD also provides user an option to save and load DPD coefficients from last transmission. Therefore, DPD could either start from scratch (unity coefficients) or a set of known coefficients. This is a very useful option if user wants to reach convergence quickly under a similar transmit operation condition.

  • Page 212: Dpd/Clgc Api Programming

    DPD TUNING AND TESTING Figure 198 describes an example setup for testing the integrated DPD with the ADRV9001 evaluation board in NB applications. (In NB applications such as TETRA, PA input should be connected to the TX1 output and PA output should be connected to RX1B.) As shown in Figure 198 , an LPF is required at the Tx1 output port to filter out the Tx harmonics before feeding the signal to PA driver (If the PA Rev.
  • Page 213 DPD can be considered as an adaptive filter which is modelled according to the behavior of the PA. As mentioned previously, the ADRV9001 default model (Model 4) consists of four taps. Each tap consists of a series of polynomial terms to fit the nonlinear behavior due to compression at higher output power.
  • Page 214 UG-1828 Preliminary Technical Data in order to suppress the spectral regrowth down to the required ACPR. It is important not to include higher order power terms than needed, which might cause the DPD unstable. DPD Model 4 consists of four taps as shown in the example tap arrangement diagram in Figure 199. The four taps can be classified into three categories: The main tap –...

  • Page 215: Clgc Target Gain Measurment

    Figure 200. CLGC Configuration Parameters 10. By determining the final gain target based on the “CLGC last gain” and “CLGC filtered gain” provided by ADRV9001, user should configure “CLGC Gain Target” as shown in the above figure. After that user should disable “CLGC Loop Open” to close the loop to allow CLGC to achieve the gain target.

  • Page 216: Dynamic Profile Switching

    7.68MSPS, 3.84MSPS and 1.92MSPS satisfy the requirements, therefore, users can perform DPS on those profiles. Note in the current release, this is the only set of profiles supported by ADRV9001 for DPS. In future releases, other profiles might be added with a limitation of the maximum total number of profiles to be 6.

  • Page 217: Perform Dps On The Fly

    () to request ADRV9001 to switch to the new profile. Once receiving this command from BBIC, ADRV9001 starts to perform switching by applying the new profile and PFIR coefficients BBIC set earlier and it will not respond to any signals on Tx_enable and Rx_enable pins.

  • Page 218: Dps Api Programming

    Figure 204: BBIC and ADRV9001 Interaction to Perform DPS DPS API PROGRAMMING Table 86 summarizes the set of ADRV9001 API commands provided for DPS. Please refer to the API doxygen document for more details. Table 86. DPS APIs DPD Rx Function Name...

  • Page 219: Dps Operations In Tes

    SSI rate will be the highest rate of all dynamic profiles. • ADRV9001 will either operate in Frequency Hopping mode or DPS mode, never both. Note those limitations might be removed or relaxed in future releases. DPS OPERATIONS IN TES TES provides a user interface for experimenting DPS.
  • Page 220 UG-1828 Preliminary Technical Data Figure 206: Performing DPS in TES Rev. PrC | Page 220 of 338...

  • Page 221: General-Purpose Input/Output And Interrupt Configuration

    The Digital and Analog GPIO pins can be used as real-time status signals that provide device status information from ADRV9001 to the baseband processor when the GPIO pins are configured as outputs, with respect to ADRV9001. When set as inputs, the GPIO pins can be used as real-time control signals that can alter the device state.

  • Page 222: Digital Gpio Operation

    ORx Enable Control ADRV9001 Receiver can be reused as observation channel through either port A or port B in TDD system, a DGPIO pin should be assigned as ORx Enable signal once the ORx channel is configured. BBIC can toggle the DGPIO in Tx RF Enabled state to enable/disable the ORx channel.
  • Page 223 A complete description of power amplifier ramp control will be provided in the user guide in the future. When the power amplifier ramp control function is used in ADRV9001, an optional digital GPIO pin can be assigned as the “power amplifier ramp control enable”...
  • Page 224 Control Out Mux Control Out Mux (sometimes referred as “Monitor out”) allows status signals within the ADRV9001 to be output to digital GPIOs, such as, AGC mode the gain change flag, gain index can be mapped to DGPIO for BBIC observation by API adi_adrv9001_Rx_GainIndex_Gpio_Configure().

  • Page 225: Analog Gpio Operation

    A complete description of RX Gain Table external control is provided in the Receiver Gain Control section in this User Guide. External LNA gain can be controlled by ADRV9001 AGPIO output, each channel has 2 AGPIO control signals and achieve up to 4 external LNA gain steps control.

  • Page 226: Interrupt

    INTERRUPT The ADRV9001 features the general purpose interrupt output pin (GP_INT), the GP_INT pin can alert the baseband processor that an important event or error regarding the device operation has occurred. These events include of unlocking of PLLs, Stream Processors errors or ARM exception, and so on.

  • Page 227: Auxiliary Converters And Temperature Sensor

    These features are included to simplify control tasks and reduce pin count requirements on the baseband processor by offloading these tasks to the ADRV9001. Example usage of the auxiliary converters include static voltage measurements performed by the AuxADC and flexible voltage control performed by the AuxDAC. This section outlines the operation of these features along with API command for configuration and control.

  • Page 228: Temperature Sensor

    ADI_ADRV9001_AUXADC3 The AuxADC clock rate is set to 30.72 MHz (or close when ADRV9001 ARM system clock is changed) to get the best ADC performance. There are no on chip calibrations executed for the AuxADC, the ADC accuracy is limited to the accuracy of the supply reference. A simplified procedure for measuring and accounting for the AuxADC gain and offset error is performed, those AuxADC gain and offset errors are used to compensate the AuxADCs measure results.

  • Page 229: Rf Port Interface Information

    EXTERNAL LO PORTS: LO1± AND LO2± Two external LO inputs (LO1 and LO2) can be applied to ADRV9001 and each external LO signal can be used for any of two receivers or two transmitters instead of internally generated LO signal. AC-coupling interface is needed for both positive and negative sides of external LO input pins which are internally biased.
  • Page 230 S(3,3) = 0.136/–156.169 S(3,3) = 0.109/–125.024 IMPEDANCE = 77.425 – j8.680 IMPEDANCE = 86.866 – j15.742 –0.2 –5.0 –0.5 –2.0 –1.0 FREQUENCY (30.000MHz TO 6.000GHz) Figure 210. ADRV9001 RX A Port Series Equivalent Differential Impedance Rev. PrC | Page 230 of 338...
  • Page 231 Data Access Component (DAC). In the below diagram Term1 is the single ended input or output and Term2 represents the differential input or output RF port on ADRV9001. The Pi on the single ended side and the differential Pi configuration on the differential side allows maximum flexibility in designing matching circuits, and is suggested for all design layouts as it can step the impedance up or down as needed with appropriate component population.

  • Page 232: General Receiver Port Interface

    Receiver Port A/B Switching ADRV9001 supports wide range of RF frequencies from 30 MHz to 6 GHz, however, typical RF balun will not support all frequencies but only cover a smaller range. There is a special feature to support switching Rx A and B ports, which allows user to use both of them as receiver channels and they can be switched at run time depending on the carrier frequency.
  • Page 233 Reasonable approximation of return loss of a frequency matching network can be obtained with a simple S parameter simulation available in ADS without PCB artwork. Figure 216 illustrates a wide-band frequency match simulation setup in ADS for ADRV9001 RX1(2) A input pins in ADS for evaluating a possible configuration for a desired match to 3 GHz.

  • Page 234: General Transmitter Bias And Port Interface

    Preliminary Technical Data S parameters for a selected balun and ac-coupling SMD type caps and ADRV9001 RX input impedance can be used to represent balun’s balanced side interface to the device. Shunt and series matching component can be added with short TLs to represent possible PCB traces associated with these matching components on the single side of balun.
  • Page 235 Preliminary Technical Data UG-1828 Transmitter Interface Configurations Tx1+/Tx2+ 1.8V Tx1 OR Tx2 OUTPUT STAGE Tx1–/Tx2– Figure 220. ADRV9001 RF Transmitter Interface Configuration A 1.8V Tx1+/Tx2+ 1.8V Tx1 OR Tx2 OUTPUT STAGE Tx1–/Tx2– 1.8V Figure 221. ADRV9001 RF Transmitter Interface Configuration B 1.8V...

  • Page 236: Impedance Matching Network Examples

    RX1A± and RX2A± Impedance Matching Network The ADRV9001 evaluation board uses both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside accommodates the larger DB1627 case style transformer.
  • Page 237 Preliminary Technical Data UG-1828 BALUN LOCATED L245 ON BOTTOM OF THE BOARD T207 TCM2-33X+ C245 R245 L246 C246 R246 L247 L219 AGND L238 C238 R238 C247 C219 BALUN LOCATED RX2A_IN+ ON TOP L216 L236 OF THE BOARD RX2A R219 R247 0805 FOOTPRINT C216 C236...
  • Page 238 UG-1828 Preliminary Technical Data L/C/R 245 L/C/R 247 L/C/R 219 C232 L/C/R L/C/R L/C/R L/C/R Frequency Balun L/C/R 246 L/C/R 248 L/C 218 L/C/R 220 L/C 221 R232 2.8 GHz – 5 Anaren L215: L216: L217: L238: L236: L245/246: L247/248: L218: L219/220: L221:...

  • Page 239: Receiver Rf Port Impedance Match Measurement Data

    Preliminary Technical Data UG-1828 Table 97. RX1B± and RX2B± Impedance Matching Network L/C/R 249 L/C/R 251 L/C/R 227 C233 L/C/R L/C/R Frequency Balun L/C 222 L/C 224 L/C/R 237 L/C/R 250 L/C/R 252 L/C 225 L/C/R 228 L/C 229 R233 30 MHz –...
  • Page 240 UG-1828 Preliminary Technical Data Figure 226. Return Loss of RX1(2)A Port Figure 227. Return Loss of RX1(2)B Port Figure 228. Insertion Loss – Simulated RX1(2)A Port – Red Curve RX1(2)B Port – Blue Curve Rev. PrC | Page 240 of 338...

  • Page 241: Transmitter Rf Port Impedance Matching Network

    TX1± and TX2± Impedance Matching Network For the TX path, the ADRV9001 evaluation board uses both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high frequency narrowband baluns while the backside accommodates the larger AT224-1A case style transformer.

  • Page 242: Transmitter Rf Port Impedance Match Measurement Data

    UG-1828 Preliminary Technical Data C346/34 C333 L309 C309 L/C/R 312 L339 C334 R367/36 L/C/R L/C/R L/C/R L310 C310 L/C/R 313 C339 C335 Frequency Balun L/C 311 R361 L/C 314 L/C 316 30 MHz – 1 MiniCircuits L311: L309/310: C309/C310 L312/313: L339: C346/34 R361: DNI...

  • Page 243: External Lo Port Impedance Matching Network

    LO frequency. Method of obtaining matching network is similar to RX and TX port matching. Depending on the selected divide ratio of ADRV9001 external LO input frequency divider SPI register setting, a band of frequency in which external LO matching network need to operate should be correctly derived by the division ratio chosen.
  • Page 244 In general, higher power level of external LO signal applied gives better phase noise to some extent. The minimum input power level that satisfy RX/TX phase noise requirements with some margin should be used. Refer to Table 100 for power level recommendation. Table 99. Specifications for ADRV9001 RF EXT LO Differential Input Pins Parameter...
  • Page 245 2nd order). The ADRV9001 provides special mode of operation for external LO in range from 500 MHz to 1000 MHz. In that region it is possible to inject external LO that will produce RF Channel frequency with x1 multiplier.

  • Page 246: External Lo Impedance Match Measurement Data

    UG-1828 Preliminary Technical Data Figure 233. External LO Impedance Matching Network Table 101. EXTLO1± and EXTLO2± Impedance Matching Network C349 L326 R356 L330/332 L333/335 L324 L325 C319 R321 C357 C362/363 C364/366 C320/321 L331 C322/323 L334 R350 Frequency Balun C317 R318 R319 R357 R326/327...

  • Page 247: Connection For External Device Clock (Dev_Clk_In)

    CONNECTION FOR EXTERNAL DEVICE CLOCK (DEV_CLK_IN) ADRV9001 can accommodate 3 different types of external clock signals applied at device clock input pins. A differential low voltage differential signaling (LVDS) clock signal or a single-ended clipped sinewave clock signal from a TCXO can be applied to the device input pins.
  • Page 248 UG-1828 Preliminary Technical Data Table 102. Device Clock Input Interface Modes Description Voltage Applied at Device Clock Input DEV_CLK_OUT Divider Value Applied MODEA Pin Electrical Interface to DEV_CLK_IN Signal Note 0 V (grounded) LVDS Up to 1GHz clock 0.45 V CMOS or XTAL CM0S(10MHz to 80MHz) /XTAL(20 MHz to 80 MHz) with...

  • Page 249: Dev_Clk_In Phase Noise Requirements

    Clock source with phase noise performance outlined in Table 104 (or better) allows ADRV9001 to deliver datasheet performance. It should be noted that Table 103 provide reference information for ADRV9001 operating with LTE type standards. Each standard will determine its own DEV_CLK phase noise requirements. As an example, Table 104 provides recommendation for DEV_CLK...

  • Page 250: Connection For Multichip Synchronization (Mcs) Input

    UG-1828 Preliminary Technical Data when ADRV9001 is intended to operate with LMR type standards. Ideally DEV_CLK phase noise requirement should be derived from customer specific application and its requirements set for adjacent channel rejection. In general, using a higher phase noise source can degrade performance delivered by ADRV9001 transceiver.

  • Page 251: Printed Circuit Board Layout Recommendations

    This section provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues. The goal of this document is to help achieve the best possible performance from the ADRV9001 while reducing board layout effort.

  • Page 252: Fan-Out And Trace Space Guidelines

    FAN-OUT AND TRACE SPACE GUIDELINES The ADRV9001 device family uses a 196-pin BGA 12 × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it impractical to route all signals on a single layer. RF pins have been placed on the outer edges of the ADRV9001 package. This helps in routing the critical signals without a fan-out via.

  • Page 253: Component Placement And Routing Priorities

    COMPONENT PLACEMENT AND ROUTING PRIORITIES The ADRV9001 transceiver requires few external components to function, but those that are needed require careful placement and routing to optimize performance. This section provides a priority order and checklist for properly placing and routing critical signals and components as well as those whose location and isolation are not as critical.
  • Page 254 • The ADRV9001 evaluation board uses microstrip lines for Rx and Tx RF traces. Some data port signal are routed using a combination of microstrip lines on the bottom of the PCB and stripline traces on internal layers due to board complexity. In general, RF traces should not use vias unless a direct line route is not possible.
  • Page 255 Matching network design is explained in greater detail in the RF Port Interface Information section of this document. • RF signal path isolation is critical to achieving the level of isolation specified in the ADRV9001 datasheet. More details on proper isolation are provided in the Isolation Techniques Used on the ADRV9001 Evaluation Card section.
  • Page 256 Figure 245 shows an example of how the ferrite beads, reservoir capacitors and decoupling capacitors should be placed. Recommendation is to connect a ferrite bead between a power plane and ADRV9001 at a distance away from ADRV9001. The ferrite bead should supply a trace with a reservoir capacitor connected to it.
  • Page 257 1.0 V analog, This approach that uses some of ADRV9001 internal LDOs to generate 1.0 V for internal blocks. For remining blocks it expect the 1.0 V to be delivered from external power source. Figure 247 outline power supply routing recommendations for this architecture.
  • Page 258 TRACE TO 1.8V DIG 4.7µF CAPACITOR Figure 247. ADRV9001 Power Supply Domains with Connection Guidelines, Some Internal LDOs bypassed, 1.0 V Analog Domain Required Ceramic 4.7 µF bypass capacitors must be placed at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0, VCLKVCO_1P0, VAUXVCO_1P0, VCONV_1P0 and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors if at all possible.

  • Page 259: Rf And Data Port Transmission Line Layout

    ALL DIGITAL GPIO SIGNALS ROUTED BELOW THE RED LINE Figure 248. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines RF AND DATA PORT TRANSMISSION LINE LAYOUT RF Line Design Summary The RF line design is a compromise between many variables. Line impedance, line to line coupling, and physical size represent the parameters subject to compromise.
  • Page 260 DIFFERENTIAL PI NETWORK Figure 249. Receiver Matching Network on ADRV9001 Evaluation Board The circuit in Figure 249 shows the layout topology for the chosen receiver matching network. Note the location and orientation of each component – placement is critical to achieve expected performance. Similarly, the circuit in Figure 250 shows the layout topology used for the transmitter matching network.
  • Page 261 Transmitter Bias and Port Interface This section considers the dc biasing of the ADRV9001 transmitter (Tx) outputs and how to interface to each Tx port. At full output power, each differential output side draws approximately 100mA of DC bias current. The Tx outputs are dc biased to a 1.8 V supply voltage using either RF chokes (wire-wound inductors) or a transformer (balun) center tap connection.
  • Page 262 Each transmitter requires approximately 200 mA supplied through an external connection. The PCB layout of the ADRV9001 board allows use of external chokes to provide 1.8 V power domain to the ADRV9001 outputs to allow users to try different baluns that may not have a dc center tap pin to supply the bias voltage to the transmitter outputs.
  • Page 263 When a Tx balun that is able to conduct dc is used then the system shown in Figure 254 should be used. The decoupling cap near the Tx balun should be placed as close as possible to the balun’s DC feed pin. Its orientation should be perpendicular to the ADRV9001 device so the return current avoids a ground loop with the ground pins surrounding the Rx input.
  • Page 264 Figure 255. Transmitter Power Supply Using RF Chokes SSI Data Port Trace Routing Recommendations The Data Port interface transfer I/Q data between BBIC/FPGA and ADRV9001 Tx and Rx datapaths. There are two possible mode of operation for SSI data port: •...
  • Page 265 Evaluation Board FMC Connector Signals Mapping The ADRV9001 evaluation board use FMC standard connector as an interface to carrier boards. Table 106 outlines signal mapping used on FMC connector implemented on ADRV9001 evaluation board. Second column refers to FMC standard pinout names. For more information refer to ADRV9001 EVB schematic.

  • Page 266: Isolation Techniques Used On The Adrv9001 Evaluation Card

    ISOLATION TECHNIQUES USED ON THE ADRV9001 EVALUATION CARD Given the density of sensitive and critical signals, significant isolation challenges are faced when designing a PCB for the ADRV9001. Isolation requirements listed below were followed to accurately evaluate the ADRV9001 device performance. Analytically determining aggressor-to-victim isolation in a system is very complex and involves considering vector combinations of aggressor signals and coupling mechanisms.
  • Page 267 When utilizing the proposed isolating structures, it is important to place ground vias around the slots and apertures. Figure 257 illustrates the methodology used on the ADRV9001 evaluation card. When slots are used, ground vias should be placed at each end of the slots and along each side.
  • Page 268 UG-1828 Preliminary Technical Data Figure 258. Shielding of Rx Launches RF IO baluns are spaced and aligned to reduce magnetic coupling from the structures in the balun package. Care must also be taken to reduce cross talk over shared grounds between baluns. Another precaution taken involved placing and orienting SMA connectors to minimize connector to connector coupling between ports.

  • Page 269: Power Supply Recommendations

    ADRV9001 by its own LDOs. This power domain, supplies voltage to noise sensitive blocks of the ADRV9001. If user intend to provide external 1.0V, care should be taken to ensure very low noise level on this power domain.

  • Page 270: Power Supply Domain Connections

    Power supply to the ADRV9001 should be delivered following star configuration where, a separate trace from a common power plane is used to power each power supply pins.
  • Page 271 Preliminary Technical Data UG-1828 Voltage Pin No. Type Pin Name Description ANALOG VAUXSYN_1P3 1.3 V Supply for Auxiliary Synthesizer. This pin is sensitive to supply noise. ANALOG VRFSYN1_1P3 1.3 V Supply for RF LO1 Synthesizer. This pin is sensitive to supply noise. ANALOG VRX1LO_1P3 1.3/1.0...

  • Page 272: Power Supply Architecture

    Switch Mode regulator (ADP5056) is used to achieve power efficiency while generating domains that supply ADRV9001. Remote sensing configuration is utilized to take in account voltage drop in filters and ensure power domains accuracy at ADRV9001 input pins.
  • Page 273 Figure 259. Power Supply Connection Diagram Power domain filtering Power signals to the ADRV9001 are further isolates from each other using C/FB/C/FB cascaded filters followed by high current ferrite beads. Figure 260 outlines at filtered approach implemented on an EVB.
  • Page 274 (where possible). This approach ensures that the voltage drop resulting from the cascaded filters and FB resistance is taken into account and the voltage level delivered to the ADRV9001 is in line with expected accuracy. In scenarios where single power domain powers multiple power pins, current tends to be distributed over multiple pins and this helps with minimizing IxR voltage drop on FB components.

  • Page 275: Rf And Clock Synthesizer Supplies

    RF channel. Refer to Figure 259 for an example of how the power supply connections are made on the ADRV9001 evaluation card. The synthesizers are more susceptible to low frequency noise than other supplies because they have programmable loop filters. The loop filter bandwidth directly affects the supply noise rejection on the synthesizers.

  • Page 276: Power Supply Configurations

    From power supply implementation point of view, the ADRV9001 can work in multiple configurations. This section outlines them in details. Depends on final application of ADRV9001 in end system user have a freedom to implement different ways to power the IC. Final solution will depend on: if external 1.0V power domain is utilized or not...
  • Page 277 Preliminary Technical Data UG-1828 Figure 263. Available modes for external 1.0V power domain and LO power supply configuration Rev. PrC | Page 277 of 338...
  • Page 278 UG-1828 Preliminary Technical Data Figure 264. Power supply modes for different number of active Tx RF IOs Rev. PrC | Page 278 of 338...
  • Page 279 Preliminary Technical Data UG-1828 Figure 265. Power supply modes for different number of active Rx and Tx RF IOs Rev. PrC | Page 279 of 338...
  • Page 280 In case where not all RF IOs or other interface pins are utilized in end application user should follow Table 109 for recommendation what to do with unused pins. Table 109. Instruction Explaining How to Handle ADRV9001 Unused Pins Pin No.
  • Page 281 Preliminary Technical Data UG-1828 Pin No. Type Mnemonic Unused instructions Input VCONV_1P8 Not applicable. Input VAGPIO_1P8 Not applicable. Input VAUXVCO_1P3 Not applicable. Input VTX1LO_1P3 Not applicable. G14, H14 Output TX1+, TX1- Do not connect. Input VANA2_1P8 Not applicable. Output VTX2LO_1P0 Connect to VSSA when unused Input AUXADC_3...

  • Page 282: Summary

    PCB applications. Deviation from these recommendations could result in sub-standard system performance that is very difficult to isolate after the system has been committed to a PCB design. Contact Analog Devices for demo board layout files and schematics that utilize many of the recommended techniques.

  • Page 283: Ldo Configurations

    ±2.5%. The LDO configurations on the ADRV9001 can affect the overall power consumption. On the ADRV9001 evaluation board all the internal LDOs are used and they generate the 1v needed for all the rails. This allows for different RF channels to be used while evaluating.
  • Page 284 UG-1828 Preliminary Technical Data Standard operating Low power operation Low power operation Configuration 0 Configuration 2 Some internal Configuration 1 Some internal All internal LDOs used LDOs bypassed, External LO LDOs bypassed, Internal LO Internal LO generation used. generation used. generation used.
  • Page 285 Input pin. The purpose of this mode is to allow the user to use higher efficiency power sources to supply the ADRV9001, as opposed to having the power overhead of associated with an LDO.
  • Page 286 UG-1828 Preliminary Technical Data CLK_PLL_SYNTH_LDO CLK_PLL_VCO_LDO CLK_PLL_LP_SYNTH_LDO 1 CLK_PLL_LP_VCO_LDO LO1_PLL_SYNTH_LDO LO1_PLL_VCO_LDO LO2_PLL_SYNTH_LDO LO2_PLL_VCO_LDO AUX_PLL_SYNTH_LDO AUX_PLL_VCO_LDO SRAM_LDO A device driver interface is implemented through the API function, adi_adrv9001_powermanagement_Configure, allowing the user to set the ldoPowerSavingsModes. The user should configure the ldoPowerSavingModes struct in adi_adrv9001_PowerManagementSettings (GUI generated code sets all modes = 1) to achieve the different power saving configurations shown in Figure 266.
  • Page 287 Preliminary Technical Data UG-1828 ADI_ADRV9001_LDO_POWER_SAVING_MODE_2, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1 } In this case it is still assumed that 2T/2R channels are still being used. If it’s the case that the user application only uses Tx1 and Rx1 then the LDOs for those channels can be set to a bypass or power down mode along with hardware modifications. There is a relationship between the hardware power layout and the LDO mode so attention is needed to correctly set the part to reflect the physical implementation.
  • Page 288 UG-1828 Preliminary Technical Data Standard operating Configuration 0 All internal LDOs used Internal LO generation used. VCONV_1P8 (G7) VAGPIO_1P8 (G8) VANA1_1P8 (H13) + External Tx1 pull-ups VANA2_1P8 (H2) + External Tx2 pull-ups VDIGIO_1P8 (M7) VDIG_1P0 (L7,L8) VDIG_0P9 (M8) 4.7µF VRFSYN1_1P3 (E11) VRFSYN2_1P3 (E4) VAUXSYN_1P3 (E10) VCLKSYN_1P3 (E5)
  • Page 289 Preliminary Technical Data UG-1828 TX_2_LO_LDO VTX2LO_1P0 Powered off, ch2 not required CLK_PLL_SYNTH_LDO Left on CLK_PLL_VCO_LDO VCLKVCO_1P0 Left on CLK_PLL_LP_SYNTH_LDO 1 Left on CLK_PLL_LP_VCO_LDO VCLKVCO_1P0 Left on LO1_PLL_SYNTH_LDO Powered off, using external LO LO1_PLL_VCO_LDO VRFVCO1_1P0 Powered off, using external LO LO2_PLL_SYNTH_LDO Powered off, LO2 not required LO2_PLL_VCO_LDO VRFVCO2_1P0...

  • Page 290: Adrv9001 Evaluation System

    SD Card Imaging To image the SD card properly for use in either the Xilinx Platform you will need to download the ADRV9001 Disk Imaging Utility and the dotNet Disk Imager. These can be found on the Engineer Zone support forum for the TES GUI & Software Support. Follow the instructions and make sure to check if there is any encryption when writing to an SD card that will prevent the FPGA from reading the card.
  • Page 291 Preliminary Technical Data UG-1828 Figure 269. Xilinx Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform Rev. PrC | Page 291 of 338...
  • Page 292 Insert the SD card that came with the ADRV9001 evaluation kit into ZYNQ ZC706 evaluation platform SD card slot (J30). On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES), at a +13dBm power level to J501 connector.
  • Page 293 The SD card included with the evaluation kit is placed in the J100 slot of the ZYNQ platform The evaluation hardware setup is shown in Figure 273. Figure 272. Xilinx ZCU102 Evaluation Board with Jumper Settings and Switch Position Configured to Work with ADRV9001 Evaluation Platform Rev. PrC | Page 293 of 338...
  • Page 294 Insert the SD card that came with the ADRV9001 evaluation kit into ZCU102 evaluation platform SD card slot (J100). On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES), at a +13dBm power level to J501 connector.

  • Page 295: Hardware Operation

    User must ensure that high quality, stable and low phase noise clock source is used here. For receiver testing on the ADRV9001 evaluation card, use a clean signal generator with low phase noise to provide an input signal to the selected Rx RF input. Use a shielded RG-58, 50Ω coaxial cable (1m or shorter) to connect the signal generator.

  • Page 296: Transceiver Evaluation Software (Tes)

    The user is expected to use the software power off feature from the TES before physically switching power off using SW1. If this advice is not followed, the file system on the SD card can get corrupted and the ADRV9001 evaluation system might stop operating.
  • Page 297 Figure 276. Software Installation Directory Starting the Transceiver Evaluation Software User can start the TES by clicking on Start -> ADRV9001 Transceiver Evaluation Software. Figure 277 shows the opening page of the TES after it is activated. Rev. PrC | Page 297 of 338...
  • Page 298 Platform is desired. Figure 278 shows an example of correct connection between a PC and a Xilinx Platform with an ADRV9001 daughter card connected to it. In this window user can check used hardware version as well as all software components versions used by the system in current TES revision.
  • Page 299 Preliminary Technical Data UG-1828 Figure 278. Setup Revision Information Configuring the Device Contained within the Device Configuration tab are setup options for the device. In this page the user can select the following: • Product: • Supports ADRV9002, ADRV9003 and ADRV9004 •...
  • Page 300 UG-1828 Preliminary Technical Data • TX supports I/Q, I/Q FM/FSK, Direct FM/FSK types • Frequency Deviation • This option is available only for TX FM type setups. • ORx1 and ORx2 can be enabled for IQ input • Interface Rate allows the user to select the rate for the interface, this can be used to over or under sample from the sample rate. The user may need to provide their own PFIR to account for this.
  • Page 301 Preliminary Technical Data UG-1828 number from the table that is copied and appended with the External Gain Control word to get the desired gain. Shown in Figure 281 the user can see that the top row is a copy of row 196 with just the external gain control changed. Figure 280.
  • Page 302 UG-1828 Preliminary Technical Data Clocks The Clocks tab (Figure 283) provides access to the settings that determine device clock configuration. This page allows the user to: • Set the device clock. • Set the device clock frequency. • Set the divisor value applied to the frequency at DEV_CLK_OUT. •...
  • Page 303 • Set the divisor value • TES informs the user about the external LO frequency that must be provided to the ADRV9001 transceiver at the External LO input. • If Internal LO is used, user has the option to select Best Phase Noise and Best Power Saving for their application. Note only Sub-1 GHz Tx frequencies are supported for Best Phase Noise option.
  • Page 304 UG-1828 Preliminary Technical Data Frequency Hopping (selected from Carrier Configuration Mode drop down menu) • For details on using the Frequency Hopping settings in the TES see the Frequency Hopping section above. Figure 285. Carriers Configuration Tab (Frequency Hopping) Figure 286. Carriers Configuration Tab (Frequency Hopping Tables) Rev.
  • Page 305 Preliminary Technical Data UG-1828 Radio The Radio tab (see Figure 287) lets the user configure the channel enablement, Tx and Rx characteristics. • Select channel control mode (hardware enable signals or API command). • Select HIGH, MED, or LOW receiver ADC rate. •...
  • Page 306 UG-1828 Preliminary Technical Data Advanced Features The Advanced Features tab (see Figure 288) provides access to the settings that determine device DPD configuration. This page allows the user to: • Multi-Chip Sync • Select from Enabled and Enabled with RF PLL Phase Sync options •...
  • Page 307 Preliminary Technical Data UG-1828 Figure 289 Synchronous Transfer option in the Transmit Tab Note the evaluation software has synchronous transfer option provided for the user. This option allows the user to begin transfer of data (through the FPGA DMA) on both channels (Tx1&Tx2 or Rx1&Rx2) at the same point in time. Its purpose is for testing MCS to ensure that both channels have the same sample at the same point in time.
  • Page 308 Rx and Tx Overview The “Rx Overview” (Figure 293) and “Tx Overview” (Figure 294) tabs aim to provide more detail on ADRV9001 selected mode of operation using “Device Configuration” tab (Figure 279). The Rx and Tx datapath overview diagrams are provided in each tab. These tabs provide user with read back of ADC/DAC sampling frequencies, analog filtering configuration, datapath sampling rate, data port format, mode of operation and sampling rate.
  • Page 309 Preliminary Technical Data UG-1828 In “Rx Overview” tab user can also read back IF frequency and observe pFIR channel filtering characteristics and their passband flatness. Quick zooming capability allows zooming of the passband response using the mouse cursor as well as restoring to the full-scale plot. The TES also provides capability to export the data plotted on the graphs to an external file.
  • Page 310 The receiver Gain Control tab (Figure 295) allows user to configure per channel, receiver gain control mode. Configuration selected in that tab is then applied to the ADRV9001 during initialization. During runtime user can change interface gain as well as if manual mode is enabled Rx gain.
  • Page 311 Preliminary Technical Data UG-1828 Figure 295. Rx Gain Control Tab Figure 296. GPIO Configuration For more detailed information refer to Rx Gain Control section of this document. The GPIO tab also shares a section with the frequency hopping as seen in Figure 285. Tx Front End Tx Attenuation Rev.
  • Page 312 UG-1828 Preliminary Technical Data • User can use DGPIO pins for TX attenuation control. User can assign DGPIO pins to attenuation increment and decrement. The step size can be specified in the “Attenuation Control” tab. Default step size is set to 0.05 dB. Tx PA Ramp •...
  • Page 313 Preliminary Technical Data UG-1828 Figure 298. Monitor Mode Window Figure 299. Power Savings and Monitor Mode Transmitter Operation Selecting the Transmit tab opens a page as shown in Figure 300. The upper plot displays the FFT of the digital data and the lower plot shows its time domain waveform.
  • Page 314 Have a frequency offset correction option. This allows user to change frequency on the air without re-programming the chip. Pressing the play symbol moves the ADRV9001 to the transmit state and starts a process where selected Data Files for the “Tx1” and “Tx2”...
  • Page 315 Preliminary Technical Data UG-1828 Receiver Operation The Receive tab opens a window as shown in Figure 301. The upper plot displays the FFT of the received input data and the lower plot shows its time domain waveform. When multiple Rx inputs are enabled, the user can select the desired data to be displayed in the Spectrum plot using the checkboxes below the plot.
  • Page 316 UG-1828 Preliminary Technical Data Captured Data Format Figure 302. Interleaving Option RX captured data can be saved using the save button next to the play button. The data is saved in either tsv or csv format. Each column corresponds to one channel. Data samples follow 1Q15 fixed point format, when the user selects the interleaved option. Shown as follows: Channel 1 | Channel 2 ----------|----------- | I1...

  • Page 317: Automated Time Division Duplexing (Tdd)

    ADRV9001 supports automatic TDD operation. User can send and receive TDD framed data by configuring this tab (see Figure 304). This of course depends on how system and setup is selected described in the previous sections. ADRV9001 comes with predefined timing configurations by default.
  • Page 318 UG-1828 Preliminary Technical Data Figure 304. Automated TDD Configuration Tab Figure 305. Automated TDD Timing Diagram TDD Parameter Table The table s auto populated by the TES based on the configuration file chosen • Enable Column • User can enable/disable receiver/transmitter channel. •...
  • Page 319 Preliminary Technical Data UG-1828 • Assert/Deassert entries are frame locations, they are not durations, for example if RX1 primary assert is 0 and primary deassert is 10000 μs, this means within the specified frame the RX1 enable is on from 0 to 10000 μs and off for the rest of the frame. •...

  • Page 320: Tracking Calibrations

    Enabling Tx1 DMA sends data from FPGA to SSI interface. Disabling Tx1 DMA stops sending data from FPGA to SSI interface. It works together with Tx_interface enabling/disabling (accepting data from SSI at ADRV9001) so it provides more flexibility for user to control what data to transmit.

  • Page 321: Digital Predistortion

    Auxiliary DAC/ADC ADRV9001 evaluation software allows user for setting Auxiliary ADC/DAC for different control or monitoring purposes. User can go to Auxiliary tab and enable Aux DAC/ADC here. For Aux DACs, user must specify a DAC code, valued from 0 ~ 4095. This effectively sets the voltage level for that Aux DAC pin.

  • Page 322: Frequency Hopping Tes Examples

    Figure 308. Auxiliary DACs and ADCs FREQUENCY HOPPING TES EXAMPLES Here we show two examples of utilizing TES to achieve frequency hopping for ADRV9001. For details on the frequency hopping operation go to the Frequency Hopping section of this document.
  • Page 323 Preliminary Technical Data UG-1828 Figure 309. Manual Frequency Hopping Example Specify the Hop Pin as Pin 01. By default it should be set to Pin 01. Specify Hop Mode. Different profiles may have certain modes enabled/disabled Mux Preprocess indicates two LOs are in use for frequency hopping, and the tables are preprocessed prior to hopping Mux Real-Time Process indicates two LOs are in use for frequency hopping, and tables are processed at the hopping stage.
  • Page 324 UG-1828 Preliminary Technical Data Figure 310. Frequency Hopping Tables The Executed Sequence is displayed in the table at the bottom of the tab. Any changes made to the frequency hopping setting will automatically populate this table to show the sequence that will be programmed. Figure 311.
  • Page 325 Preliminary Technical Data UG-1828 Tx Only 11. Change the Tx Data Source Single Tone, in the main TES window, and put 0 Hz under Tone 1 Frequency. You should see figure Figure 312. Manual Frequency Hopping Using TES This indicates vi.
  • Page 326 UG-1828 Preliminary Technical Data The current frame is being played for frequency 1000 MHz, highlighted as blue. Next frame is assigned as Tx as well. Signal should appear at Tx output as 1000.001 MHz single tone. 14. Repeat the last step. Figure 315.
  • Page 327 Preliminary Technical Data UG-1828 Figure 316. Separate Gain and Attenuation Tables When the tables are loaded the user can enable an upload sequence in the Control Hopping by GPIO section shown in Figure 317. This CSV file contains a row of integers from 0 to 7 in the sequence that the user wants. The integer 0 will correspond to the gain and attenuation value used in the table shown in Figure 316.
  • Page 328 To achieve this, Follow the steps above before programming In Automated TDD tab, click Enable Automated TDD State Machine for FPGA ADRV9001 TES includes several pre-defined examples in the /Examples folder. Rx Only Select the pre-defined json file DMR_24K_RX_ONLY_FH.json Hop Pin should be set automatically.
  • Page 329 Preliminary Technical Data UG-1828 Note in the time domain, TES only shows actual data frames, that is without gap between data frames. Figure 320. Rx TDD DMR with Frequency Hopping Tx Only Steps are the same as Rx Only, except the pre-defined json file must be DMR_24K_TX_ONLY_FH.json We use 0 Hz tone as an example, here we see the 6 frequencies, the plot is done with max hold.
  • Page 330 IronPython is an implementation of the Python programming language targeting the .NET Framework. The IronPython editor is in the View menu and allows the user to use IronPython to write a unique sequence of events and then execute them using the ADRV9001 evaluation system.

  • Page 331: Radio State

    Power/Temperature Monitoring The ADRV9001 evaluation software allows user to monitor power usage of the system. On top there is a button Power / Temp Monitoring, which shows detailed voltage, current and power status of each power domain. It also shows the temperature from an internal temp sensor.

  • Page 332: Driver Debugger

    UG-1828 Preliminary Technical Data Figure 324. Power / Temperature Monitoring Window Driver Debugger A driver debugger is available from the View menu. This is a live window that captures all the driver calls being used by the TES. This can be used for debugging issues or understanding driver calls needed.

  • Page 333: Log File

    Preliminary Technical Data UG-1828 Log File On top of the GUI, there is a button Log File, which shows logging information of the system. If the PC is connected to the evaluation platform, log file will show the version numbers for different component of the system, including firmware, FPGA, API and so on If errors occur, for example programming the chip fails, log file will provide certain debugging information on what is failing.

  • Page 334: Automatically Generate Initialisation Code

    Check if the board is properly powered. There should be 12V present at the J22 input, and after powering the Xilinx platform on (SW1 turned on) the following should be true: Fan on the ZYNQ platform is activated. Ensure that fan cable is reconnected to ADRV9001 evaluation platform fan header P702.
  • Page 335 User may experience program failure due to init calibration. This is usually caused by Rx input is connected to the signal generator and RF output is ON. This causes ADRV9001 to interfere with its own internal Rx calibration. User should turn off RF signal during programming.
  • Page 336 UG-1828 Preliminary Technical Data Note the lack of a new line between the last two includes. This may or may not flag an error. Or you may see this: Now note the lack of “adi_” at the beginning of the final include. This is an old include used in previous revisions of the SDK, however as of version 11.0 this include is no longer valid and attempting it will cause a fatal error during compilation.
  • Page 337 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
  • Page 338 UG-1828 Preliminary Technical Data Rev. PrC | Page 338 of 338...

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