Target Receive Register; Target Transmit Register; Hardware General Call Id Register; First Target Address Device Id Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: I
Table 293. Bit Descriptions for SSTAT (Continued)
Bits Bit Name Settings
3 SRXREQ
2 STXREQ
1 STXUR
0 STXFSEREQ

TARGET RECEIVE REGISTER

Address: 0x40003030, Reset: 0x0000, Name: SRX
Table 294. Bit Descriptions for SRX
Bits Bit Name
[15:8] Reserved
[7:0] SRX

TARGET TRANSMIT REGISTER

Address: 0x40003034, Reset: 0x0000, Name: STX
Table 295. Bit Descriptions for STX
Bits Bit Name
[15:8] Reserved
[7:0] ISTX

HARDWARE GENERAL CALL ID REGISTER

Address: 0x40003038, Reset: 0x0000, Name: ALT
Table 296. Bit Descriptions for ALT
Bits Bit Name Settings
[15:8] Reserved
[7:0] ALT

FIRST TARGET ADDRESS DEVICE ID REGISTER

Address: 0x4000303C, Reset: 0x0000, Name: ID0
analog.com
2
C
Description
Target Receive Request. This bit asserts whenever the target receive FIFO is not empty. Read or flush
the target receive FIFO to clear this bit. This bit asserts on the falling edge of the I2C_SCL clock pulse
that clocks in the last data bit of a byte. This bit can drive an interrupt.
Target Transmit Request. If SCTL, Bit 5 = 0, this bit is set when the direction bit for a transfer is received
high. As long as the transmit FIFO is not full, this bit remains asserted. Initially, this bit is asserted on
the negative edge of the SCL pulse that clocks in the direction bit (if the device address matches). If
SCTL, Bit 5 = 1, this bit is set when the direction bit for a transfer is received high. As long as the
transmit FIFO is not full, this bit remains asserted. Initially, this bit is asserted after the positive edge of
the I2C_SCL pulse that clocks in the direction bit (if the device address matches). This bit is cleared on
a read of the SSTAT register.
Target Transmit FIFO Underflow. This bit is set if an initiator requests data from the device, and the
transmit FIFO is empty for the rising edge of SCL.
Target Transmit FIFO Status or Early Request. If SCTL, Bit 5 = 0, this bit is asserted whenever the
target transmit FIFO is empty. If SCTL, Bit 5 = 1, this bit is set when the direction bit for a transfer
is received high. This bit asserts on the positive edge of the I2C_SCL clock pulse that clocks in the
direction bit if the device address matches. This bit only asserts once for a transfer and is cleared when
read if SCTL, Bit 5 is asserted.
Settings
Settings Description
Reserved.
Target Transmit Register.
Description
Reserved.
Target Alternative. This register is used in conjunction with SCTL, Bit 3 to match an initiator generating
a hardware general call. This register is used when an initiator device cannot be programmed with the
address of a target, and instead the target must recognize the address of the initiator.
Description
Reserved.
Target Receive Register.
ADuCM356
Reset Access
0x0 RC
0x0 RC
0x0 RC
0x1 R/W
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
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