Cyclic Voltammetry - Analog Devices ADuCM356 Reference Manual

Reference Manual
USE CASE CONFIGURATIONS
setting
BITM_HSTIA_CTIA_1PF, // inter►
nal load of 1pF
0);
tection diodes disconnected
If the high-speed TIA is selected as the ADC input channel, it is as
follows:
AfeAdcChan(MUXSELP_HSTIA_P,
MUXSELN_HSTIA_N);
HSTIA output as ADC input versus HSTIA_N to
the ADC
If the sensor output pin is connected to the diagnostic electrodes
(DE0 or DE1), the user can reduce the R
To generate sharp voltage transients on the sensor bias voltage,
open SW12 and SW13 (as shown in
the low-power DAC outputs, V
100 nF filter capacitors. Configure LPTIASWx, Bits[13:12] = 00,
LPDACCON0, Bit 5 = 1, and LPDACSW0 = 0x32.
To configure the switches in the potentiostat for the pulse test, set
LPTIASWx, Bits[11:0] = 0x094 to use the high-speed TIA. See the
analog.com
// pro►
// Select
value to <100 Ω.
LOAD
Figure 16) to disconnect
, and V from the external
BIAS ZERO
Exiting Cyclic Voltammetry Mode
decrease the settling time of the sensor when exiting pulse testing.

CYCLIC VOLTAMMETRY

Cyclic voltammetry is similar to the pulse test, except that both
the V and V outputs of the low-power DAC can change to
BIAS ZERO
set the sensor bias voltage and the common-mode voltage of the
sensor to different levels. Use the high-speed TIA for the current
output measurement from the sensor, rather than the low-power
TIA.
To generate sharp voltage transients on the sensor bias voltage,
open SW12 and SW13 (as shown in
low-power DAC outputs and V
100 nF filter capacitors. Configure LPTIASWx, Bits[13:12] = 00,
LPDACCON0, Bit 5 = 1, and LPDACSW0 = 0x32 to open SW12
and SW13.
To configure the switches in the potentiostat loop for the ramp test
with the high-speed TIA, set LPTIASWx, Bits[11:0] = 0x094. See
Figure 39 for switch setup as a result of this configuration.
To capture the full current transient of each step in the voltammetry
cycle, it may be necessary to optimize the ADC filter settings for
speed rather than noise performance.
ADuCM356
section for recommendations to
Figure 16) to disconnect the
and V from the external
BIAS ZERO
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