Register Summary: Clock Architecture - Analog Devices ADuCM356 Reference Manual

Reference Manual

REGISTER SUMMARY: CLOCK ARCHITECTURE

Table 3. Digital Die System Clock Register Summary (CLKG0_CLK Stack)
Address Name
0x4004C10C KEY
0x4004C110 CTL
0x4004C300 CTL0
0x4004C304 CTL1
0x4004C314 CTL5
0x4004C318 STAT0
Table 4. Analog Die Clock Register Summary (AFECON Stack)
Address Name
0x400C0408 CLKCON0
0x400C0410 CLKEN1
0x400C0414 CLKSEL
0x400C041C GPIOCLKMUXSEL
0x400C0420 CLKCON0KEY
0x400C0A70 CLKEN0
0x400C0A0C OSCKEY
0x400C0A10 OSCCON
0x400C20BC HPOSCCON
0x400C22F0 PMBW
analog.com
Description
Key protection for CTL register
Oscillator control
Clock Control 0
Clock dividers
User clock gating control
Clocking status
Description
Clock divider configuration
Clock gate enable
Clock select
GPIO clock mux select to GPIO1 pin
Key protection for CLKCON0
Clock control of low-power TIA chop, watchdog, and wake-up timers
Key protection for OSCCON
Oscillator control
High-power oscillator configuration
Power mode configuration register
ADuCM356
Reset Access
0x00000000 R/W
0x00000302 R/W
0x00000078 R/W
0x00100404 R/W
0x0000001F R/W
0x00000000 R/W
Reset
0x0441
0x010A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0303
0x00000024
0x00000000
Rev. A | 15 of 312
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W