Analog Devices ADuCM356 Reference Manual page 265

Reference Manual
DIGITAL DIE GENERAL-PURPOSE TIMERS
Interval = (GPTx_LOAD × Prescaler)/Clock Source
For example, if GPTx_LOAD = 0x100, prescaler = 4, and clock
source = high frequency oscillator, the interval is 39.38 µs (where
high frequency oscillator = 26 MHz).
If the timer is set to count up,
Interval = ((Full Scale − GPTx_LOAD) × Prescaler)/Clock
Source
Asynchronous Clock Source
Timers are started by setting the enable bit (GPTx_CTL, Bit 4) to
1 in the control register of the corresponding timer. However, when
the timer clock source is the low frequency oscillator, the following
precautions must be taken.
Do not write to GPTx_CTL if GPTx_STAT, Bit 6 is set.
►
GPTx_STAT must be read prior to configuring GPTx_CTL. When
GPTx_STAT, Bit 6 is cleared, the register can be modified, ensur-
ing that synchronizing the timer control between the processor
and the timer clock domains is complete. GPTx_STAT, Bit 6 is
the timer busy status bit.
After clearing the interrupt in GPTx_CLRINT, ensure that the
►
register write has completed before returning from the interrupt
handler. Use the data synchronization barrier (DSB) instruction if
necessary and check that GPTx_STAT, Bit 7 = 0, as follows:
__asm void asmDSB()
{
nop
DSB
BX LR
}
Table 341. Capture Event Function
Event Select Range Bits, CON0, Bits[12:8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
analog.com
(29)
(30)
Timer 0 Capture Source
WUT
SYS_WAKE
Reserved
Reserved
Reserved
Reserved
DVDD_REG
Reserved
Reserved
GPIO Interrupt A
GPIO Interrupt B
General-Purpose Timer 1
General-Purpose Timer 1
Flash controller
Reserved
Reserved
The value of a counter can be read at any time by accessing
►
its value register (GPTx_CURCNT). In an asynchronous configu-
ration, GPTx_CURCNT must always be read twice. If the two
readings are different, this register must be read a third time to
determine the correct value.
GPTx_STAT must be read prior to writing to any timer register
after setting or clearing the enable bit. When GPTx_STAT, Bit 7 is
cleared, registers can be modified, which ensures that the timer has
completed synchronization between the processor and the timer
clock domains. The typical synchronization time is two timer clock
periods.
The GPTx_CTL register enables the counter, selects the mode,
selects the prescale value, and controls the event capture function.
Capture Event Function
The general-purpose timers can capture several interrupt events.
These events are shown in Table
associated with a general-purpose timer can cause a capture of
the 16-bit GPTx_CURCNT register into the 16-bit GPTx_CAPTURE
register. GPTx_CTL has a 5-bit field that can select which event to
capture.
When the selected interrupt event occurs, the GPTx_CURCNT
register is copied into the GPTx_CAPTURE register. When
GPTx_STAT, Bit 1 is set, it indicates that a capture event is
pending. The bit is cleared by writing 1 to GPTx_CLRINT, Bit 1.
The GPTx_CAPTURE register also holds its value and cannot be
overwritten until a 1 is written to GPTx_CLRINT, Bit 1.
Timer 1 Capture Source
UART
SPI0
Reserved
SPI1
2
I C target
2
I C initiator
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYS_WAKE
Reserved
General-Purpose Timer 0
General-Purpose Timer 2
ADuCM356
341. Any one of the events
Timer 2 Capture Source
SYS_WAKE
Reserved
Reserved
Reserved
DMA error
WUT
General-Purpose Timer 0
General-Purpose Timer 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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