Register Summary: Dma - Analog Devices ADuCM356 Reference Manual

Reference Manual

REGISTER SUMMARY: DMA

Table 196. DMA Register Summary
Address Name
0x40010000 STAT
0x40010004 CFG
0x40010008 PDBPTR
0x4001000C ADBPTR
0x40010014 SWREQ
0x40010020 RMSK_SET
0x40010024 RMSK_CLR
0x40010028 EN_SET
0x4001002C EN_CLR
0x40010030 ALT_SET
0x40010034 ALT_CLR
0x40010038 PRI_SET
0x4001003C PRI_CLR
0x40010048 ERR_CLR
0x4001004C ERRCHNL_CLR
0x40010050 INVALIDDESC_CLR
0x40010800 BS_SET
0x40010804 BS_CLR
0x40010810 SRCADDR_SET
0x40010814 SRCADDR_CLR
0x40010818 DSTADDR_SET
0x4001081C DSTADDR_CLR
0x400C2008 FIFO_CON
0x400C206C DATAFIFORD
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Description
Status
Configuration
Channel primary control data base pointer
Channel alternate control data base pointer
Channel software request
Channel request mask set
Channel request mask clear
Channel enable set
Channel enable clear
Channel primary alternate set
Channel primary alternate clear
Channel priority set
Channel priority clear
Bus error clear
Per channel bus error
Per channel invalid descriptor clear
Channel bytes swap enable set
Channel bytes swap enable clear
Channel source address decrement enable set
Channel source address decrement enable clear
Channel destination address decrement enable set
Channel destination address decrement enable clear
FIFO configuration
Data FIFO read
ADuCM356
Reset Access
0x00180000 R
0x00000000 W
0x00000000 R/W
0x00000200 R
0x00000000 W
0x00000000 R/W
0x00000000 W
0x00000000 R/W
0x00000000 W
0x00000000 R/W
0x00000000 W
0x00000000 W
0x00000000 W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 W
0x00000000 R/W
0x00000000 W
0x00000000 R/W
0x00000000 W
0x00001010 R/W
0x00000000 R
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