Dma Controller; Dma Features; Dma Overview; Dma Analog Die - Analog Devices ADuCM356 Reference Manual

Reference Manual

DMA CONTROLLER

The DMA controller is used to perform data transfer tasks between
peripherals and memory locations to offload these tasks from the
microcontroller unit (MCU). Data can be moved quickly by the DMA
without CPU actions, keeping the CPU free for other operations.

DMA FEATURES

The ADuCM356 provides dedicated and independent DMA chan-
nels. There are two programmable priority levels for each DMA
channel. Each priority level arbitrates using a fixed priority that
is determined by the DMA channel number. Channels with lower
numbers have higher priority. For example, SPI0 transmit has the
highest priority, and the next highest priority is the SPI0 receive.
Table 188. DMA Channel Assignment
Channel Number
0
1
2, 3, 6, 7, 13, 14
4
5
8
9
10
11
12
15
16
17
18 to 23

DMA ANALOG DIE

The ADC on the AFE die can be connected to the DMA controller.
An eight-word FIFO is provided to buffer. The output of the FIFO is
the DMA controller. The user can select from the following inputs:
ADC sinc3 result (16 bits)
►
DFT result, real first followed by imaginary part (18 bits for each
►
device)
ADC sinc2 and low-pass filter result (16 bits)
►
ADC mean result (16 bits)
►
AFE Die Data FIFO
DMA Channel 17 is associated with the AFE die data FIFO. To
enable this die, write 1 to FIFOCON, Bit 12. When the FIFO is
enabled (FIFOCON, Bit 11 = 1) and FIFOCON, Bit 12 = 1, the FIFO
issues a DMA request any time the FIFO is not empty.
Program Flow
After performing the following steps, the data FIFO issues DMA
requests whenever the FIFO receives data. If the number of bytes
transferred matches the value specified by Bits[13:4] of the control
data configuration register (CFG), the DMA_DONE internal interrupt
analog.com
Each DMA channel can access a primary or alternate channel
control structure. Multiple DMA transfer types are supported, such
as the following:
Memory to memory.
►
Memory to peripheral.
►
Peripheral to memory.
►

DMA OVERVIEW

The DMA controller has 20 channels in total. The 20 channels are
dedicated to managing DMA requests from specific peripherals.
Channels are assigned, as shown in
Peripheral Description
SPI1 transmit
SPI1 receive
Reserved
SPI0 transmit
SPI0 receive
UART0 transmit
UART0 receive
I2C target transmit
I2C target receive
I2C initiator
Flash
Software DMA
AFE die ADC
Software DMA
is asserted. To set up the DMA controller for a particular DMA
channel, follow these steps:
1. Enable the DMA controller by setting Bit 0 of CFG to 1.
2. Enable the DMA data FIFO channel and set Bit 17 of CFG to
EN_SET.
3. Configure the DMA control description for the data FIFO chan-
nel. Refer to the
4. Select the source for data FIFO (FIFOCON, Bits[15:13]).
5. Set FIFOCON, Bit 11 and FIFOCON, Bit 12 to enable the FIFO
and DMA requests.
6. Enable the DMA_DONE interrupt.

DMA ARCHITECTURAL CONCEPTS

The DMA channel provides a means to transfer data between
memory spaces or between memory and a peripheral using the
system interface. The DMA channel provides an efficient means
of distributing data throughout the system, freeing up the core for
other operations. Each peripheral that supports DMA transfers has
its own dedicated DMA channel or channels with their own register
sets that configure and control the operating modes of the DMA
transfers.
ADuCM356
Table 188.
Channel Control Data Structure
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section.