Register Details: Crc; Crc Control Register; Input Data Word Register; Crc Result Register - Analog Devices ADuCM356 Reference Manual

Reference Manual

REGISTER DETAILS: CRC

CRC CONTROL REGISTER

Address: 0x40040000, Reset: 0x10000000, Name: CTL
Table 405. Bit Descriptions for CTL
Bits Bit Name Settings
[31:28] REVID
[27:5] Reserved
4 W16SWP
3 BYTMIRR
2 BITMIRR
1 LSBFIRST
0 EN

INPUT DATA WORD REGISTER

Address: 0x40040004, Reset: 0x00000000, Name: IPDATA
Table 406. Bit Descriptions for IPDATA
Bits Bit Name
[31:0] VALUE

CRC RESULT REGISTER

Address: 0x40040008, Reset: 0x00000000, Name: RESULT
Table 407. Bit Descriptions for RESULT
Bits Bit Name
[31:0] VALUE

PROGRAMMABLE CRC POLYNOMIAL REGISTER

Address: 0x4004000C, Reset: 0x04C11DB7, Name: POLY
Table 408. Bit Descriptions for POLY
Bits Bit Name
[31:0] VALUE

INPUT DATA BITS REGISTER

Address: 0x40040010 to 0x40040017 (Increments of 0x01), Reset: 0x00, Name: IPBITSN
analog.com
Description
Revision ID.
Reserved.
Word 16 Swap. This bit swaps 16-bit half words within a 32-bit word.
0 Word 16 swap disabled.
1 Word 16 swap enabled.
Byte Mirroring. This bit swaps 8-bit bytes within each 16-bit half word.
0 Byte mirroring is disabled.
1 Byte Mirroring is enabled.
Bit Mirroring. This bit swaps bits within each byte.
0 Bit mirroring is disabled.
1 Bit mirroring is enabled.
LSB First Calculation Order.
0 MSB first CRC calculation.
1 LSB first CRC calculation.
CRC Peripheral Enable.
0 CRC peripheral is disabled.
1 CRC peripheral is enabled.
Settings
Settings
Settings Description
CRC Reduction Polynomial.
Description
Data Input.
Description
CRC Reset.
ADuCM356
Reset Access
0x1 R
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
Reset Access
0x0 W
Reset Access
0x0 R/W
Reset Access
0x4C11DB7 R/W
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