Raw Result Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: ADC CIRCUIT
Table 64. Bit Descriptions for ADCFILTERCON (Continued)
Bits Bit Name
[11:8] SINC2OSR
7 AVRGEN
6 SINC3BYP
5 Reserved
4 LPFBYPEN
[3:1] Reserved
0 ADCCLK

RAW RESULT REGISTER

Address: 0x400C2074, Reset: 0x00000000, Name: ADCDAT
This register is the ADC result register for raw ADC output or when sinc3 filter options are selected.
Table 65. Bit Descriptions for ADCDAT
Bits Bit Name Settings
[31:16] Reserved
[15:0] DATA
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Settings Description
1 Oversampling rate of 4. Use for 400 kHz sinc3 filter output update rate. Use when ADC update
rate is 1.6 MSPS. High-power option.
10 Oversampling rate of 2. Use for 400 kHz sinc3 filter output update rate. Use when ADC update
rate is 800 kSPS.
11 Reserved. Do not use this setting.
Sinc2 Filter Oversampling Rates.
0 22 samples for this OSR setting.
1 44 samples for this OSR setting.
10 89 samples for this OSR setting.
11 178 samples for this OSR setting.
100 267 samples for this OSR setting.
101 533 samples for this OSR setting.
110 640 samples for this OSR setting.
111 667 samples for this OSR setting.
1000 800 samples for this OSR setting.
1001 889 samples for this OSR setting.
1010 1067 samples for this OSR setting.
1011 1333 samples for this OSR setting.
Enable ADC Average Function.
0 Disable average.
1 Enable average. Average result feeds to next stage.
Sinc3 Filter Bypass.
0 Sinc3 filter active. Enable sinc3 filter.
1 Bypass sinc3 filter. Raw 800 kHz or 1.6 MHz ADC output data is fed directly to gain offset
adjustment stage. If the sinc3 filter is bypassed, the 200 kHz sine wave can be handled directly
by DFT block without amplitude attenuation. If the sinc3 filter is bypassed and ADC raw data
rate is 800 kHz, the gain offset block output is used as DFT input.
Reserved.
50 Hz or 60 Hz Low-Pass Filter. Bypass both 50 Hz and 60 Hz notch filter.
1 Bypass both 50 Hz notch and 60 Hz notch filters.
0 Enable 50 Hz notch and 60 Hz notch filters. ADC result is written to the SINC2DAT register.
Reserved.
ADC Data Rate. Unfiltered ADC output rate.
1 800 kHz.
0 1.6 MHz. If ADC sample rate is 1.6 MHz, ADC clock frequency must be 32 MHz.
Description
Reserved.
ADC Result. Register contains the ADC conversion result. Depending on user configuration, result can
reflect raw or sinc3 filter outputs. The result is a 16-bit unsigned number.
ADuCM356
Reset Access
0x3 R/W
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R
0x1 R/W
Reset Access
0x0 R
0x0 R/W
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