Sram Retention In Hibernate Mode; Sram Initialization - Analog Devices ADuCM356 Reference Manual

Reference Manual
SRAM
If SRAM_CTL, Bit 31 is 0 and cache is disabled, the 64 kB of
SRAM is mapped as data SRAM. The memory is arranged in two
sections. The first (32 kB) is mapped at Start Address 0x20000000
and the second (32 kB) at 0x20040000 (see Mode 2 in
If cache memory feature is used, the second section only maps 28
kB. Therefore, the total data SRAM available is 60 kB (see Mode 3
in Figure 54).
By default, at power-up and hardware reset, the 32 kB of SRAM is
made available as instruction SRAM. If the user must use a total of
64 kB data SRAM, SRAM_CTL, Bit 31 must be programmed to 0
at the start of the user code. When the cache controller is enabled,
SRAM Bank 5 is not accessible. A bus error (unmapped address) is
generated if an access is attempted.

SRAM RETENTION IN HIBERNATE MODE

The amount of SRAM retained during the hibernate mode var-
ies based on user configuration. The content of the first 8 kB
(Bank 0) of data SRAM is mapped at 0x20000000 and is always
retained. The SRAM mapped from 0x20040000 onwards (Bank 3,
Bank 4, and Bank 5) cannot be retained in the hibernate mode.
If SRAM_CTL, Bit 1 is enabled, 8 kB of data SRAM mapped
from 0x20002000 to 0x20003FFF (Bank 1) is retained in the hiber-
nate mode. If SRAM_CTL, Bit 31 = 1 and SRAM_CTL, Bit 2 is
enabled, 16 kB of instruction SRAM mapped from 0x10000000 to
0x10003FFF (Bank 2) is retained. If SRAM_CTL, Bit 31 = 0, 16
kB of data SRAM mapped from 0x20004000 to 0x20007FFF is
retained.
SRAM Programming Model, Stack
The SRAM start address is set to 0x20000000 and the stack pointer
is set at 0x20002000. The stack is written from 0x20001FFF down-
ward. The covered memory region is always retained. To reserve a
given size for the stack area, the user can declare a data array of
that desired size ending at Position 0x20001FFF so that the stack is
not overwritten by the compiler when allocating new variables.
SRAM Parity
For robustness, parity check can be enabled on all or a user
selected group of SRAM banks. Parity check can detect up to
two errors per word. The parity check feature can be enabled by
asserting SRAM_CTL, Bits[5:0] for each SRAM bank. The kernel
enables these bits by default.
Parity is checked when data is read and when byte or half word
data is written. Parity is not checked when a word write (32 bits)
is performed. If a parity error is detected, a bus error is generated.
Even if parity error is detected when writing a byte or half word, the
write operation is completed and parity bits are updated according
to the new data. The user must manage the parity error in the bus
fault interrupt routine.
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SRAM INITIALIZATION

If parity check is enabled, SRAM contents must be initialized
to avoid false parity errors. A dedicated hardware feature can
Figure 54).
automatically initialize the selected SRAM banks. This process
takes 1024 HCLK cycles to complete. This hardware is fully pro-
grammable by the user, and as such, initialization can be started
automatically or manually.
Initialization overwrites the contents of the selected SRAM banks.
Therefore, initialization must be performed before writing to those
SRAM blocks. If, during the initialization sequence, a write or read
access to a SRAM bank being initialized is detected, the access is
pending until the initialization sequence is completed. SRAM banks
that are not selected to be initialized can be accessed as usual
during the initialization process of the rest of the banks.
The initialization for a particular SRAM bank can be monitored for
its completion by polling the appropriate SRAM_INITSTAT, Bits[5:0]
in the SRAM_INITSTAT read only register. Every time a particular
SRAM bank is initialized, its associated SRAM_INITSTAT, Bits[5:0]
are cleared and remain low until initialization is completed.
After power-up, SRAM Bank 0 (8 kB) is automatically initialized.
This memory is always retained and contains the stack pointer and
critical information. Bank 0 contents do not have to be overwritten in
the future, because initialization has already been performed. Avoid
initializing SRAM banks that are already initialized, because they
may already contain user information.
Initialization of more SRAM banks, where parity is enabled, can
be achieved at any time by writing to the SRAM_CTL register.
Set the appropriate SRAM_CTL, Bits[5:0] for SRAM banks that
need parity to be enabled to 1. Also, set SRAM_CTL, Bit 13 to
1. SRAM_CTL, Bit 13 is autocleared to 0 after being written and
triggers the initialization sequence.
After exiting hibernate mode, the contents of nonretained SRAM
banks are lost. If these banks have parity enabled, initialization
is required. There are two options to initialize the required SRAM
banks after exiting hibernate mode as follows:
Initialize by writing to SRAM_CTL, Bit 13 after exiting hibernate
►
mode. The SRAM banks that are set to 1 by SRAM_CTL,
Bits[5:0] are initialized.
Automatic initialization after hibernate mode. There is no write re-
►
quired to SRAM_CTL after hibernate mode. To select automatic
mode, set SRAM_CTL, Bit 14 prior to hibernation or initialization.
The SRAMs selected for initialization in this register automatical-
ly initialize after exiting hibernate mode.
Initialization resets the contents of the selected memory banks. It
is important that the user carefully select which memory banks are
initialized so no user information is lost. The initialization sequence
can be aborted at any time by writing to SRAM_CTL, Bit 15. This bit
is self cleared after it has been written.
ADuCM356
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