Fifo Configuration Register; Data Fifo Read Register - Analog Devices ADuCM356 Reference Manual

Reference Manual
REGISTER DETAILS: DMA

FIFO CONFIGURATION REGISTER

Address: 0x400C2008, Reset: 0x00001010, Name: FIFOCON
Table 219. Bit Descriptions for FIFOCON
Bits Bit Name
[31:16] Reserved
[15:13] DATAFIFOSRCSEL
12 DATAFIFODMAREQEN
11 DATAFIFOEN
[10:0] Reserved

DATA FIFO READ REGISTER

Address: 0x400C206C, Reset: 0x00000000, Name: DATAFIFORD
Table 220. Bit Descriptions for DATAFIFORD
Bits Bit Name Settings
[31:25] ECC
[24:18] Reserved
[17:0] DATAFIFOOUT
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Settings Description
Reserved.
Selects the Source for the Data FIFO.
000, 001, 110, ADC data. ADC data is output of sinc3 filter.
111
010 DFT data, 18-bit real part and 18-bit imaginary part.
011 Sinc2 output.
100 Statistic variance output.
101 Statistics mean result.
Enable Data FIFO DMA Channel.
0 Disable DMA requests for data FIFO.
1 Enable DMA requests for data FIFO.
Data FIFO Enable.
0 FIFO is reset. No data transfers may take place. Sets the read and write pointers to
the default values (empty FIFO). Status indicates if FIFO is empty.
1 Normal operation. FIFO is not reset.
Reserved.
Description
ECC of Lower 25 Bits.
Reserved.
Data FIFO Read. If data FIFO is empty, a read of this register returns 0x00000000.
ADuCM356
Reset Access
0x0 R
0x0 R/W
0x1 R/W
0x0 R/W
0x10 R
Reset Access
0x0 R
0x0 R
0x0 R
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