Adc Circuit Operation; Adc Transfer Function - Analog Devices ADuCM356 Reference Manual

Reference Manual
ADC CIRCUIT
The ADC has a number of postprocessing features, as follows:
Digital filtering of sinc2 and sinc3, and 50 Hz or 60 Hz power
►
supply rejection.
DFT, used with impedance measurements to automatically calcu-
►
late magnitude and phase values.
Programmable averaging of ADC results.
►
Programmable statistics option for calculating the mean.
►
Multiple calibration options to support system calibration of the
►
current, voltage, and temperature channels.
The ADC input stage provides an input buffer to support low input
current and low input leakage specifications on all channels.
To support a range of current and voltage based input ranges,
the ADC front end provides a PGA and programmable TIAs. The
PGA supports gains of 1, 1.5, 2, 4, and 9. The low-power TIAs
support programmable gain resistors ranging from 200 Ω to 512 kΩ.
The high-speed TIA, used for impedance measurement, supports
programmable gain resistors ranging from 200 Ω to 160 kΩ.
The default reference source of the ADC is a precision, low drift,
internal 1.8 V reference source. Optionally, connect an external
reference to the VREF_1.82V and AGND_REF pins.
The ADC supports averaging and digital filtering options. With these
options, the user can trade off speed and precision. The highest
ADC update rate is 800 kHz in low-power mode or 1.6 MSPS in
high-power mode with no digital filtering. The ADC filtering options
also include a 50 Hz or 60 Hz mains power supply filter. When
Figure 9. Ideal ADC Transfer Function, Voltage Input to ADC vs. Output Codes, Where Input is ADCVBIAS_CAP at 1.11 V
To calculate the input voltage (V
convert ADC codes to a voltage:
For PGA gain = 1,
V = (VREF × (((ADCDAT − 0x8000)/2
IN
BIAS_CAP
For PGA gain = 1.5,
V = (VREF/1.5 × (((ADCDAT − 0x8000)/2
IN
+ ADCVBIAS_CAP
For PGA gain = 2, 4, or 9,
analog.com
), use the following equation to
IN
15
))) + ADCV-
15
) × 1.835/1.82))
the mains power supply filter is enabled, the ADC update rate is
typically 900 Hz. If no filtering is selected, the supported resolution
reduces to 14 bits.
The ADC supports a number of postprocessing features. These
features include a DFT calculator. The DFT is intended for impe-
dance measurements to remove the processing requirements from
the microcontroller. Minimum, maximum, and mean value detec-
tions are also supported.

ADC CIRCUIT OPERATION

The SAR ADC is based on a charge redistribution DAC. The capac-
itive DAC consists of two identical arrays of 16 binary weighted
capacitors that are connected to the two inputs of the comparator.
The ADC block operates from the 16 MHz clock in normal oper-
ation. This clock ensures a maximum ADC update rate of 800
kSPS with no filtering. For high-power mode, select the 32 MHz
oscillator as the ADC clock source. The ADC maximum update rate
is 1.6 MSPS with higher power consumption. For normal mode and
high-power mode, it is strongly recommended to enable the sinc3
filter option at a minimum, which results in a 200 kSPS.

ADC TRANSFER FUNCTION

The transfer function in
on the y-axis and the differential voltage into the ADC. The ADC
negative input channel is the 1.11 V voltage source (ADCCON,
Bits[12:8] = 0b01000). The positive input channel is any voltage
input to the ADC after the TIA, PGA, and input buffer stages.
V = (VREF/PGA_GAIN × (((ADCDAT − 0x8000)/2
IN
ADCVBIAS_CAP
where:
VREF = 1.82 V (typical).
ADCDAT is the ADC conversion result.
(1)
ADCVBIAS_CAP = 1.11 V (typical).
PGA_GAIN is the PGA gain setting minus one. This gain is set by
ADCCON, Bits[18:16].
(2)
ADuCM356
Figure 9 shows the ADC output codes
15
))) +
Rev. A | 54 of 312
(3)