Power Management Unit; Power Management Unit Features; Power Management Unit Operation - Analog Devices ADuCM356 Reference Manual

Reference Manual

POWER MANAGEMENT UNIT

POWER MANAGEMENT UNIT FEATURES

The ADuCM356 contains two separate PMUs, one for each die.
The PMUs control the different power modes of each ADuCM356
die.
The power management features of the device include the follow-
ing:
High efficiency buck converters to reduce power on the digital
►
die.
Buck converter for active mode, which requires external flying
►
capacitors, as shown in the
disabled by default. For optimal performance of the analog
peripherals, leave the converter disabled.
The DC-DC converter shown on the digital die is optional.
►
If disabled, the three capacitors connected to the VDCDC_x
pins are not required and these five pins can be left uncon-
nected.
Customized clock gating for active modes.
►
Power gating to reduce leakage in sleep modes.
►
Voltage monitoring.
►
Flexible sleep modes with smart peripherals.
►
Deep sleep modes with no retention.
►
Three power modes are available: active mode, flexi mode, and
hibernate mode. The power mode control for each die is separate.
analog.com
Figure 3. Power Supply Architecture Block Diagram
Figure 3. The buck converter is
Active Mode
The Arm Cortex-M3 is executing from flash and SRAM on the
digital die. PMG0 PWRMOD, Bits[1:0] = 00. The analog die circuitry
is in active mode. ALLON PWRMOD, Bits[1:0] = 01.
Flexi Mode
In this mode, the Arm Cortex-M3 is disabled. The user selects the
peripherals to be enabled, for example, SPI for DMA or I
DMA.
Hibernate Mode
On the digital die, the system is power gated. 8 kB of SRAM is
always retained. Up to an additional 24 kB SRAM can be selected
to be retained. PMG0 PWRMOD, Bits[1:0] = 10.
On the analog die, the high-speed oscillator and high-speed clock
source are powered down so that all blocks clocked by these clock
sources are clock gated. The 32 kHz oscillator and the analog die
watchdog timer remains active. Optionally, the low-power DACs,
low-power reference, and low-power amplifiers can remain active to
keep an external sensor biased. ALLON PWRMOD, Bits[1:0] = 10.

POWER MANAGEMENT UNIT OPERATION

The debug tools can prevent the Arm Cortex-M3 from fully entering
power saving modes by setting bits in the debug logic. Only a
ADuCM356
2
C for
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