Crc Data Transfer; Crc Interrupts And Exceptions; Crc Programming Model - Analog Devices ADuCM356 Reference Manual

Reference Manual
CYCLIC REDUNDANCY CHECK

CRC DATA TRANSFER

The data stream can be written to the block using the DMA control-
ler or by using the MCU directly.

CRC INTERRUPTS AND EXCEPTIONS

The DMA channel generates an interrupt upon completion of data
transfer to the CRC block.

CRC PROGRAMMING MODEL

The CRC block is provided to calculate the CRC signature over
a block of data in the background while the core performs other
tasks. The CRC block supports two modes of CRC calculation: core
access and DMA access.
Core Access Steps
To access the core, take the following steps:
1. Program the POLY register with the required polynomial justi-
fied, as detailed in the Polynomial
2. Program the result register with the initial seed. The seed must
be justified and written to the result register, as detailed in the
Polynomial section.
3. Enable accelerator function by writing to the CTL register.
Note that the following steps require a single write to the CTL
register:
a. Set the EN bit high.
b. Modify the W16SWP, BYTMIRR, and BITMIRR bits in the
CTL register, which configure the application with different
mirroring options. For more information, see the
Options section.
c. Set or reset the LSBFIRST bit to indicate whether to use
LSB first or MSB first in CRC calculation.
The core can start sending data to the CRC block by writing
into the IPDATA register. The CRC accelerator continues to
calculate the CRC as long as data is written to the IPDATA
register. It is the responsibility of the application to count the
number of words written to the CRC block. After all the words
are written, the application can read the result register.
4. Read the result register. This register contains the x-bit result in
x MSB bits for MSB first and in x LSB bits for LSB first CRC
calculation.
5. Calculate CRC on the next data block. To calculate the CRC on
the next block of data, repeat Step 1 to Step 4.
6. Disable the CRC accelerator block by clearing the EN bit in CTL
to ensure that the block is in a low-power state.
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Mirroring
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