Arm Cortex-M3 Processor; Arm Cortex-M3 Processor Features; Arm Cortex-M3 Processor Operation - Analog Devices ADuCM356 Reference Manual

Reference Manual

ARM CORTEX-M3 PROCESSOR

The ADuCM356 contains an embedded Arm Cortex-M3 processor.
The Arm Cortex-M3 processor provides a high performance, low
cost platform that meets the system requirements of minimal mem-
ory implementation, reduced pin count, and low-power consump-
tion, and delivers computational performance and system response
to interrupts.

ARM CORTEX-M3 PROCESSOR FEATURES

The high performance features of the Arm Cortex-M3 processor are
as follows:
A 26 MHz maximum clock speed.
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256 kB of embedded flash memory with error correction code
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(ECC).
32 kB system SRAM with parity.
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32 kB user configurable instruction or data SRAM with parity. 4
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kB of SRAM can be used as cache memory to reduce active
power consumption by reducing access to flash memory.
1.25 Dhrystone million instructions per second (DMIPS)/MHz.
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Many instructions are single cycle, including multiply.
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Separate data and instruction buses allow simultaneous data
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and instruction accesses to be performed.
Optimized for single cycle flash usage.
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A flexible RTC that supports a wide range of wake-up times.
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Three general-purpose timers and one watchdog timer.
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Programmable GPIOs, each with optional input interrupt capabili-
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ty.
The low-power features are as follows:
PMU.
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POR and PSM.
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Buck converter for improved efficiency during active state.
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The core is implemented using advanced clock gating so that
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only the actively used logic consumes dynamic power.
Power saving mode support (hibernate mode). The design has
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separate clocks to allow unused parts of the processor to be
stopped.
The advanced interrupt handling features are as follows:
The NVIC supports up to 240 interrupts. The ADuCM356 sup-
►
ports 64 of these interrupts. The vectored interrupt feature
greatly reduces interrupt latency because there is no need for
software to determine which interrupt handler to serve. Addition-
ally, there is no need to have software to set up nested interrupt
support.
The Arm Cortex-M3 processor automatically pushes registers
►
onto the stack at the entry interrupt and retrieves them at the
exit interrupt. Pushing and retrieving reduces interrupt handling
latency and allows interrupt handlers to be normal C functions.
Dynamic priority control for each interrupt.
►
Latency reduction using late arrival interrupt acceptance and tail
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chain interrupt entry.
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Immediate execution of an NMI request for safety critical applica-
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tions.
The system features are as follows:
Support for bit band operation and unaligned data access.
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Advanced fault handling features include various exception types
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and fault status registers.
The debug support features are as follows:
Serial wire debug (SWD) port.
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Flash patch and breakpoint (FPB) unit for implementing break-
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points. Limited to two hardware breakpoints.
Data watchpoint and trigger (DWT) unit for implementing watch-
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point trigger resources and system profiling. Limited to one
hardware watchpoint. The DWT does not support data matching
for watchpoint generation because it has only one comparator.

ARM CORTEX-M3 PROCESSOR OPERATION

Several Arm Cortex-M3 processor components are flexible in their
implementation. This section details the implementation of these
components in the ADuCM356.
Serial Wire Debug
The ADuCM356 only supports the serial wire interface via the
SWCLK and SWDIO pins. The device does not support the 5-wire,
Joint Action Test Group (JTAG) interface. The SWCLK pin is driven
by the debug probe. The SWDIO signal is a bidirectional signal
that can be driven by the debug probe or target, depending on the
protocol phase.
NVIC
The Arm Cortex-M3 processor includes an NVIC, which offers
several features, as follows:
Nested interrupt support
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Vectored interrupt support
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Dynamic priority changes support
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Interrupt masking
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In addition, the NVIC has an NMI input. The NVIC is implemented
on the ADuCM356, and more details are available in the
Exceptions and Peripheral Interrupts
Wake-Up Interrupt Controller
The ADuCM356 has a modified WIC that provides the lowest
possible power-down current. See the
section for details.
It is not recommended to enter power saving mode when servicing
an interrupt. However, if the device enters power saving mode
when servicing an interrupt, it can only be woken up by a higher
priority interrupt source.
ADuCM356
System
section.
Power Management Unit
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