Analog Devices ADuCM310 Manuals

Manuals and User Guides for Analog Devices ADuCM310. We have 1 Analog Devices ADuCM310 manual available for free PDF download: Hardware Reference Manual

Analog Devices ADuCM310 Hardware Reference Manual

Analog Devices ADuCM310 Hardware Reference Manual (192 pages)

Brand: Analog Devices | Category: Motherboard | Size: 2 MB

Table of Contents

Functional Block Diagram
1
Scope
1
Table of Contents
2
Revision History
4
Using the Aducm310 Hardware Reference Manual
5
Introduction to the Aducm310
6
- Main Features of the Aducm310
  7
- Memory Organization
  8
Clocking Architecture
9
Power Management Unit
14
ARM Cortex-M3 Processor
17
ADC Circuit
19
- ADC Circuit Block Diagram
  19
- ADC Circuit Features
  19
- ADC Circuit Overview
  19
- ADC Circuit Operation
  20
- ADC Transfer Function
  20
- ADC Input Buffer
  22
- ADC Typical Setup Sequence
  22
- ADC Internal Channels
  23
- ADC Support Circuits
  24
- Register Summary: ADC Circuit
  27
- Register Details: ADC Circuit
  28
  - 3/2016-Rev. 0 to Rev. a Changes to Table 18
    30
  - 6/2019-Rev. a to Rev. B Added Table 44 Title
    48
  - REVISION HISTORY 3/2020-Rev. B to Rev. C Change to Table 127
    97
  - Digital Inputs/Outputs
    98
  - Digital Inputs/Outputs Block Diagram
    98
  - Digital Inputs/Outputs Features
    98
  - Digital Inputs/Outputs Overview
    98
  - Change to Table 130
    99
  - Digital Inputs/Outputs Operation
    99
  - Digital Port Multiplex
    100
  - Register Summary: Digital Input/Output
    102
  - Register Details: Digital Input/Output
    103
  - C Operation
    110
  - C Serial Interface
    110
  - I 2 C Features
    110
  - I 2 C Overview
    110
  - I 2 C Operating Modes
    112
  - Register Summary: I 2 C0
    114
  - Register Details: I 2 C0
    115
  - Register Summary: I 2 C1
    124
  - Register Details: I 2 C1
    125
  - Serial Peripheral Interfaces
    134
  - SPI Features
    134
  - SPI Operation
    134
  - SPI Overview
    134
  - SPI Transfer Initiation
    135
  - SPI Interrupts
    137
  - SPI CSERR Condition
    138
  - Spi Dma
    138
  - Spi Wire-Or'ed Mode (Wom)
    138
  - SPI and Power-Down Modes
    139
  - Register Details: SPI0
    140
  - Register Summary: SPI0
    140
  - Changes to Table 201
    141
  - Register Details: SPI1
    144
  - Register Summary: SPI1
    144
  - UART Features
    148
  - UART Operation
    148
  - UART Overview
    148
  - UART Serial Interface
    148
  - Register Details: UART
    152
  - Register Summary: UART
    152
  - General-Purpose Timers
    157
  - General-Purpose Timers Block Diagram
    157
  - General-Purpose Timers Features
    157
  - General-Purpose Timers Overview
    157
  - General-Purpose Timers Operation
    158
  - Register Details: General-Purpose Timer 0
    160
  - Register Summary: General-Purpose Timer 0
    160
  - Register Details: General-Purpose Timer 1
    163
  - Register Summary: General-Purpose Timer 1
    163
  - Register Details: General-Purpose Timer 2
    166
  - Register Summary: General-Purpose Timer 2
    166
  - Register Summary: Watchdog Timer
    169
  - Watchdog Timer
    169
  - Watchdog Timer Block Diagram
    169
  - Watchdog Timer Features
    169
  - Watchdog Timer Operation
    169
  - Watchdog Timer Overview
    169
  - Register Details: Watchdog Timer
    170
  - Wake-Up Timer
    172
  - Wake-Up Timer Block Diagram
    172
  - Wake-Up Timer Features
    172
  - Wake-Up Timer Operation
    172
  - Wake-Up Timer Overview
    172
  - Register Details: Wake-Up Timer
    174
  - Register Summary: Wake-Up Timer
    174
  - Pulse Width Modulation (PWM)
    178
  - PWM Features
    178
  - PWM Operation
    178
  - PWM Overview
    178
  - PWM Interrupt Generation
    180
  - Register Details: PWM
    181
  - Register Summary: PWM
    181
  - PLA Features
    185
  - PLA Overview
    185
  - Programmable Logic Array (PLA)
    185
  - PLA Operation
    186
  - Register Details: PLA
    189
  - Register Summary: PLA
    189
- Register Details: VDAC
  49
- Register Summary: VDAC
  49
- System Exceptions and Peripheral Interrupts
  56
- Reset
  65
  - Register Summary: Reset
    65
  - Reset Features
    65
  - Reset Operation
    65
  - Register Details: Reset
    66
- DMA Controller
  67
  - DMA Features
    67
  - DMA Operation
    67
  - DMA Overview
    67
  - Channel Control Data Structure
    68
  - DMA Priority
    68
  - Interrupts
    68
  - Control Data Configuration
    69
  - DMA Transfer Types (CHNL_CFG[2:0])
    70
  - Aborting DMA Transfers
    72
  - Address Calculation
    72
  - Register Details: DMA
    73
  - Register Summary: DMA
    73
- Changes to Protection, Integrity Section
  78
- Flash Controller
  79
  - Flash Controller Features
    79
  - Flash Controller Overview
    79
  - Flash Controller Operation
    80
  - Flash Memory Operation
    81
- Added ECC Error Handling Section
  81
- Added ECC Error During Read Section and ECC Error During Execution of Sign Command
  82
- Silicon Identification
  97
  - Register Details: Silicon Identification
    97
  - Register Summary: Silicon Identification
    97
Register Details: Additional Registers
32
Register Summary: Additional Registers
32
Idacs
34
- IDAC Features
  34
- IDAC Block Diagram
  34
- IDAC Overview
  34
- Register Summary: IDAC
  40
- Register Details: IDAC
  40
Vdacs
46
- VDAC Features
  46
- VDAC Block Diagram
  46
- VDAC Overview
  46
- VDAC Operation
  47

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