Analog Devices ADuCM355 Hardware Reference Manual
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Analog Devices ADuCM355 Hardware Reference Manual

Analog Devices ADuCM355 Hardware Reference Manual

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ADuCM355
Hardware Reference Manual
UG-1262
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADuCM355
Hardware Reference Manual

SCOPE

This manual provides a detailed description of the
ADuCM355
functionality and features. See the
ADuCM355
data sheet for the
functional block diagram.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
Rev. B | Page 1 of 312
WARNING AND LEGAL TERMS AND CONDITIONS.

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Summary of Contents for Analog Devices ADuCM355

  • Page 1: Scope

    ADuCM355 Hardware Reference Manual UG-1262 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com ADuCM355 Hardware Reference Manual SCOPE This manual provides a detailed description of the ADuCM355 functionality and features. See the...

  • Page 2: Table Of Contents

    Revision History ................9 Power Mode Register ..............31     Using the ADuCM355 Reference Manual ........11 Key Protection for PWRMOD and SRAMRET Register ..31   Introduction to the ADuCM355 ..........12 Control for Retention SRAM During Hibernate Mode  ...
  • Page 3 ADuCM355 Hardware Reference Manual UG-1262   ADC, High Speed DAC, and Associated Amplifiers Offset Calibration High Speed TIA Channel Register ..78   Operating Mode Configuration ..........52   Gain Calibration for High Speed TIA Channel Register ..78  ...
  • Page 4 UG-1262 ADuCM355 Hardware Reference Manual Low Power TIA Switch Configuration for Channel 0 Register DAC Offset with Attenuator Disabled (Low Power Mode)     ....................... 94 Register ..................114   Low Power TIA Control Bits Channel 1 Register ....95 DAC Offset with Attenuator Enabled (High Power Mode)  ...
  • Page 5 ADuCM355 Hardware Reference Manual UG-1262     Sleep and Wake-Up Timer Features ........145 Channel Primary Alternate Clear Register ......180     Sleep and Wake-Up Timer Overview ........145 Channel Priority Set Register ..........180     Configuring a Defined Sequence Order ....... 145 Channel Priority Clear Register ..........
  • Page 6 C Operation ................226   Serial Wire Debug Enable Register ........213   C Operating Modes ............... 228   Analog Devices Identification (Analog Die) Register ..213   Register Summary: I C ..............231   Chip Identification (Analog Die) Register ......213  ...
  • Page 7 ADuCM355 Hardware Reference Manual UG-1262     First Master Address Byte Register ........234 UART Serial Interface ..............256     Second Master Address Byte Register ........234 UART Overview ................ 256     Serial Clock Period Divisor Register ........235 UART Features ................
  • Page 8 UG-1262 ADuCM355 Hardware Reference Manual     Analog Die General-Purpose Timers Features ....274 WUT Functional Description ..........287     AFE PWM ................. 274 WUT Operating Modes ............288     Register Summary: Analog Die General-Purpose Timers ..275 WUT Recommendations: Clock and Power ......

  • Page 9: Revision History

    ADuCM355 Hardware Reference Manual UG-1262 REVISION HISTORY 2/2020—Rev. A to Rev. B Changes to Electrochemical Amperometric Measurement Section ..............90 Changed PLCC_CACHE to PLCC ......Throughout Changes to Table 9 ................20 Change to Electrochemical Impedance Spectroscopy Section ..............91 Changes to Power Management Unit Features Section ....
  • Page 10 UG-1262 ADuCM355 Hardware Reference Manual Added Interrupt Registers Section, Table 174, Interrupt Polarity Changes to Table 255 ..............217 Register Section, Table 175, Interrupt Clear Register Section, Changes to Figure 58 ..............227 and Table 176 ................140 Changes to Automatic Clock Stretching Section ..... 229 Added Interrupt Controller Select Registers Section Change to Performing SPI DMA Master Receive Section ..

  • Page 11: Using The Aducm355 Reference Manual

    ADuCM355 Hardware Reference Manual UG-1262 USING THE ADuCM355 REFERENCE MANUAL Table 1. Number Notations Notation Description Bit N Bits are numbered in little endian format, where the least significant bit of a number is referred to as Bit 0. V[x:y] A range from Bit x to Bit y of a value or a field (V) is represented in bit field format, V[x:y].

  • Page 12: Introduction To The Aducm355

    The package is 6 mm × 5 mm, 72-lead land grid array (LGA) package, and the temperature range is −40°C to +85°C. A low cost development system and a third party compiler and emulator tool support are included in the ADuCM355 evaluation kit.
  • Page 13 ADuCM355 Hardware Reference Manual UG-1262 0x400C_23FF AFE DIE REGISTERS 0x400C_0800 0x4004_4FFF DIGITAL DIE REGISTERS 0x4000_0000 0x2000_7FFF (MAPPABLE) SRAM 0x2000_0000 0x1000_7FFF (MAPPABLE) SRAM 0x1000_0000 0x0001_FFFF FLASH MEMORY 0x0000_0000 UNUSED ADDRESS SPACE Figure 1. Arm Cortex-M3 Memory Map Diagram Rev. B | Page 13 of 312...

  • Page 14: Clocking Architecture

    UG-1262 ADuCM355 Hardware Reference Manual CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE OPERATION ADuCM355 contains two internal die. Therefore, there are two independent clock systems: a digital die clock system and an analog die clock system. Figure 2 shows the overall clock architecture.

  • Page 15: Clock Gating

    ADuCM355 Hardware Reference Manual UG-1262 DIGITAL DIE RTC1 FREQUENCY FREQUENCY OSCILLATOR INTERNAL BEEPER OSCILLATOR 32kHz HPBUCK CLK 200kHz HPBUCK 13MHz RCLK DIV2 FLASH HCLK DIV HIGH CLK CTL1 RESERVED FREQUENCY [5:0] HIGH OSCILLATOR FREQUENCY CTL5[4] ROOT_CLK INTERNAL C UCLK OSCILLATOR...
  • Page 16 UG-1262 ADuCM355 Hardware Reference Manual To connect and select the AFE die 16 MHz oscillator as the external clock input for the digital die, perform the following steps: Enable AFE die Pad P2.2 as an output. pADI_AGPIO2->OEN |= 0x4; Configure the internal digital die Pad P1.10 as an input and configure its mode as EXT_CLKIN.

  • Page 17: Register Summary: Clock Architecture

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: CLOCK ARCHITECTURE Table 3. Digital Die System Clock Register Summary (CLKG0_CLK Stack) Address Name Description Reset Access 0x4004C10C Key protection for CTL register 0x00000000 0x4004C110 Oscillator control 0x00000302 0x4004C300 CTL0 Clock Control 0...

  • Page 18: Register Details: Clock Architecture

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: CLOCK ARCHITECTURE KEY PROTECTION FOR CTL REGISTER Address: 0x4004C10C, Reset: 0x00000000, Name: KEY Table 5. Bit Descriptions for KEY Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. 0x0000 [15:0] VALUE 0xCB14 Oscillator Key.

  • Page 19: Clock Dividers Register

    ADuCM355 Hardware Reference Manual UG-1262 CLOCK DIVIDERS REGISTER Address: 0x4004C304, Reset: 0x00100404, Name: CTL1 The clock dividers register is used to set the divide rates for the HCLK, PCLK, and ACLK dividers. This register can be written to at any time.

  • Page 20: Clocking Status Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access GPIOCLKOFF GPIO Clock Control. This bit disables the GPIO clock and controls the gate on the ACLK out from ACLK divider. This ACLK control is available in active mode and Flexi™...

  • Page 21: Clock Divider Configuration Register

    ADuCM355 Hardware Reference Manual UG-1262 CLOCK DIVIDER CONFIGURATION REGISTER Address: 0x400C0408, Reset: 0x0441, Name: CLKCON0 User must write CLKCON0KEY = 0xA815 before writing to CLKCON0. Table 11. Bit Descriptions for CLKCON0 Bits Bit Name Settings Description Reset Access [15:6] Reserved Reserved.

  • Page 22: Clock Select Register

    UG-1262 ADuCM355 Hardware Reference Manual CLOCK SELECT REGISTER Address: 0x400C0414, Reset: 0x0000, Name: CLKSEL Table 13. Bit Descriptions for CLKSEL Bits Bit Name Settings Description Reset Access [15:4] Reserved Reserved. [3:2] ADCCLKSEL Select ADC Clock Source. To configure the GPIO1 pin for an external clock, pADI_AGPIO2->CON |= 3<<2;...

  • Page 23: Clock Control Of Low Power Tia Chop, Watchdog, And Wake-Up Timers Register

    ADuCM355 Hardware Reference Manual UG-1262 CLOCK CONTROL OF LOW POWER TIA CHOP, WATCHDOG, AND WAKE-UP TIMERS REGISTER Address: 0x400C0A70, Reset: 0x0000, Name: CLKEN0 Table 16. Bit Descriptions for CLKEN0 Bits Bit Name Settings Description Reset Access [15:3] Reserved Reserved. TIACHPDIS TIA Chop Clock Disable.

  • Page 24: High Power Oscillator Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access HFOSCEN High Frequency Oscillator Enable. This bit is used to enable or disable the oscillator. The oscillator must be stable before use. This bit must be set before the SYSRESETREQ system reset can be initiated.

  • Page 25: Power Management Unit

    ADuCM355 Hardware Reference Manual UG-1262 POWER MANAGEMENT UNIT DIGITAL DIE DVDD DIGITAL BUCK DIE 3V CONVERTOR MAIN DIGITAL DIE 3V SUPPLY DVDD POWER SUPPLY FOR FLASH AND OTHER DIGITAL BLOCKS 2.8V TO 3.6V POWER SUPPLY AVDD_DD FOR DIGITAL DIE OSCILLATOR,...

  • Page 26: Power Management Unit Operation

    UG-1262 ADuCM355 Hardware Reference Manual Flexi Mode In this mode, the Arm Cortex-M3 is disabled. The user selects the peripherals to be enabled, for example, SPI for DMA or I C for DMA. Hibernate Mode On the digital die, the system is power gated. 8 kB of SRAM is always retained. Up to an additional 24 kB SRAM can be selected to be retained.

  • Page 27: Code Examples

    ADuCM355 Hardware Reference Manual UG-1262 CODE EXAMPLES Enter Power Saving Mode The following function configures the analog die operating mode: uint32_t AfePwrCfg(uint16_t iMode) // PSWFULLCON[14:13]= [11]b //Close switches NL and NL2. PSWFULLCON[11:10]= [11]b pADI_AFE-> PSWFULLCON|=0x6C00; // Close PL2, PL1, P12, P11 switches to tie HSTIA N and D //terminals to 1.8 V LDO...

  • Page 28: Monitor Voltage Control

    ADuCM355 provides a number of features to help user code monitor the AVDD and DVDD supply rails of the ADuCM355. On the digital die, voltage supervisory circuits are enabled at all times to guarantee that the AVDD_DD supply (2.8 V to 3.6 V) and the regulated supply are always within operating levels.

  • Page 29: Register Summary: Power Management Unit

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: POWER MANAGEMENT UNIT Table 21. Digital Die Power Management Register Summary (PMG0 Stack) Address Name Description Reset Access 0x4004C000 Power supply monitor interrupt enable 0x00000000 0x4004C004 PSM_STAT Power supply monitor status 0x2100 0x4004C008...

  • Page 30: Register Details: Power Management Unit

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: POWER MANAGEMENT UNIT POWER SUPPLY MONITOR INTERRUPT ENABLE REGISTER Address: 0x4004C000, Reset: 0x00000000, Name: IEN Table 23. Bit Descriptions for IEN Bits Bit Name Settings Description Reset Access [31:11] Reserved Reserved. 0x00000 IENBAT Interrupt Enable for AVDD_DD Range.

  • Page 31: Power Mode Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access RANGE1 AVDD_DD Range 1 (>2.75 V). This is a write one to clear status bit indicating the R/W1C relevant AVDD_DD range. Generates the AVDD_DD range interrupt if IEN, Bit 10 is set.

  • Page 32: Control For Retention Sram During Hibernate Mode Register

    UG-1262 ADuCM355 Hardware Reference Manual CONTROL FOR RETENTION SRAM DURING HIBERNATE MODE REGISTER Address: 0x4004C014, Reset: 0x00000000, Name: SRAMRET Table 27. Bit Descriptions for SRAMRET Bits Bit Name Settings Description Reset Access [31:2] Reserved Reserved. BNK2EN Enable Retention Bank 2 (16 kB). Bank address is 0x10000000 to 0x10003FFF if SRAM_CTL, Bit 31 = 1.

  • Page 33: Initialization Status Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access PENBNK1 Enable Parity Check for SRAM Bank 1. SRAM Address 0x20002000 to Address 0x20003FFF. Parity is checked when data is read and when a byte or half word data is written to this SRAM area.

  • Page 34: Power Modes Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access BNK3 Initialization Status of SRAM Bank 3. Not initialized. Initialization completed. BNK2 Initialization Status of SRAM Bank 2. Not initialized. Initialization completed. BNK1 Initialization Status of SRAM Bank 1.

  • Page 35: Arm Cortex-M3 Processor

    ADuCM355 Hardware Reference Manual UG-1262 ARM CORTEX-M3 PROCESSOR ADuCM355 contains an embedded Arm Cortex-M3 processor. The Arm Cortex-M3 processor provides a high performance, low cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, and delivers computational performance and system response to interrupts.

  • Page 36: Arm Cortex-M3 Processor Operation

     Dynamic priority changes support  Interrupt masking In addition, the NVIC has an NMI input. The NVIC is implemented on the ADuCM355, and more details are available in the System Exceptions and Peripheral Interrupts section. Wake-Up Interrupt Controller ADuCM355 has a modified WIC that provides the lowest possible power-down current.

  • Page 37: System Resets

    ADuCM355 Hardware Reference Manual UG-1262 SYSTEM RESETS There are three primary reset sources on the digital die, as shown in Figure 4. A digital die watchdog timer is also available, but is disabled by default. These reset sources are as follows: ...
  • Page 38 UG-1262 ADuCM355 Hardware Reference Manual Table 33. Digital Die Reset Implications Reset External Reset All MMRs Pins to Default Execute Except RST_STAT Reset All Valid RST_STAT Register After Reset Reset State Kernel Register Peripherals SRAM Event Software Yes/No RST_STAT, Bit 3 = 1...

  • Page 39: Register Summary: System Resets

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: SYSTEM RESETS Table 34. Digital Die Reset Register Summary Address Name Description Reset Access 0x4004C040 RST_STAT Digital die reset status 0x000000XX R/W1C Table 35. Always On Register Summary Address Name Description Reset Access...

  • Page 40: Register Details: System Resets

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: SYSTEM RESETS DIGITAL DIE RESET STATUS REGISTER Address: 0x4004C040, Reset: 0x000000XX, Name: RST_STAT Table 37. Bit Descriptions for RST_STAT Bits Bit Name Settings Description Reset Access [15:6] Reserved Reserved. [5:4] PORSRC POR Source for Digital Die. This bit contains additional details after a POR occurs.

  • Page 41: Programming, Protection, And Debug

    To save power, users can disable the internal pull-up resistor and reconfigure these pins as tristate. Take care when reconfiguring these pins from their default state, because this reconfiguration disables debug access to the ADuCM355. It is recommended to only disable the SWCLK and SWDIO feature of these pins in user code when code development and debugging is almost complete.

  • Page 42: System Exceptions And Peripheral Interrupts

    UG-1262 ADuCM355 Hardware Reference Manual SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS CORTEX-M3 AND FAULT MANAGEMENT ADuCM355 integrates an Arm Cortex-M3 processor, which supports several system exceptions and interrupts generated by peripherals. Table 40 lists the Arm Cortex-M3 processor system exceptions. Table 40. System Exceptions...
  • Page 43 ADuCM355 Hardware Reference Manual UG-1262 Wake Up From Exception Number IRQx Vector Flexi Hibernate IRQ16 SPI1 IRQ17 C slave IRQ18 C master IRQ19 DMA Error IRQ20 DMA Channel 0 done IRQ21 DMA Channel 1 done IRQ22 DMA Channel 2 done...

  • Page 44: Interrupt Sources From The Analog Die

    UG-1262 ADuCM355 Hardware Reference Manual Internal to the Arm Cortex-M3 processor, the highest user-programmable priority (0) is treated as fourth priority after a reset, an NMI, or a hard fault. The ADuCM355 implements three priority bits, which means that eight priority levels are available as programmable priorities.

  • Page 45: Clearing Analog Die Interrupt Sources

    ADuCM355 Hardware Reference Manual UG-1262 Table 42. Analog Die Interrupts List Exception Interrupt Enable Interrupt Enable Interrupt Status Interrupt Status Number IRQx Register Register Bit Register Register Bit IRQ48 ADCINTIEN ADCRDYIEN ADCINTSTA ADCRDY DFTRDYIEN DFTRDY SINC2RDYIEN SINC2RDY TEMPRDYIEN TEMPRDY ADCMINFAILIEN...

  • Page 46: Cortex-M3 Nvic Register List

    UG-1262 ADuCM355 Hardware Reference Manual CORTEX-M3 NVIC REGISTER LIST The registers in Table 43 are found in the Arm Cortex-M3. Table 43. NVIC Registers Analog Devices Address Header File Name Description Access 0xE000E004 ICTR Shows the number of interrupt lines that the NVIC supports.

  • Page 47: External Interrupt Configuration

    ADuCM355 Hardware Reference Manual UG-1262 EXTERNAL INTERRUPT CONFIGURATION Two external interrupts are implemented, separate from those described in the Digital Inputs and Outputs section. One of these external interrupts is the P1.0/SYS_WAKE pin. The other is the interrupt source from the analog die that connects to External Interrupt 3 line of the digital die, which can be connected to the UART input pin (P0.11/UART_SIN).

  • Page 48: Register Summary: System Exceptions And Peripheral Interrupts

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS Table 44. Digital Die External Interrupts Register Summary Address Name Description Reset Access 0x4004C080 XINT_CFG0 External interrupt Configuration 0 0x00200000 0x4004C084 XINT_EXT_STAT External wake-up interrupt status 0x00000000 0x4004C090...

  • Page 49: Register Details: System Exceptions And Peripheral Interrupts

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS EXTERNAL INTERRUPT CONFIGURATION 0 REGISTER Address: 0x4004C080, Reset: 0x00200000, Name: XINT_CFG0 Table 46. Bit Descriptions for XINT_CFG0 Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. [23:21] UART_RX_MDE External Interrupt Using P0.11/UART_SIN Wake-Up Mode.

  • Page 50: External Wake-Up Interrupt Status Register

    UG-1262 ADuCM355 Hardware Reference Manual EXTERNAL WAKE-UP INTERRUPT STATUS REGISTER Address: 0x4004C084, Reset: 0x00000000, Name: XINT_EXT_STAT Table 47. Bit Descriptions for XINT_EXT_STAT Bits Bit Name Settings Description Reset Access [31:6] Reserved Reserved. Interrupt Status Bit for P0.11/UART_SIN Wake-Up Interrupt. Read only STAT_UART_RXWKUP register bit.

  • Page 51: Analog Die Interrupt Enable Register

    ADuCM355 Hardware Reference Manual UG-1262 ANALOG DIE INTERRUPT ENABLE REGISTER Address: 0x400C0A28, Reset: 0x0000, Name: EI2CON Table 50. Bit Descriptions for EI2CON Bits Bit Name Settings Description Reset Access [15:4] Reserved Reserved. BUSINTEN Bus Interrupt Detection Enable Bit. Set before entering hibernate to enable the AFE wakeup via any analog die access.

  • Page 52: Analog Die Circuitry Summary

    UG-1262 ADuCM355 Hardware Reference Manual ANALOG DIE CIRCUITRY SUMMARY ADuCM355 analog die includes the following eight main blocks:  ADC. The ADC is a high speed SAR ADC with a wide range of voltage and current input channels. See the ADC Circuit section.
  • Page 53 ADuCM355 Hardware Reference Manual UG-1262 2.5V LPDAC0 LPTIA0 AIN0 TO AIN7 2.5V LPDAC1 INTERNAL CHANNELS LPTIA1 P NODE N NODE RCAL0 POSTPROCESSING: DIGITAL FILTERS, 1.82V DFT, CALIBRATION RCAL1 CE0, CE1, GAIN HSDAC AIN0 SWITCH RCAL0, SE1, AIN0 TO AIN3/BUF_VREF1V8 AIN1...

  • Page 54: Register Summary: Analog Die Circuitry

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: ANALOG DIE CIRCUITRY Table 51. Analog Die Circuitry Register Summary Address Name Description Reset Access 0x400C2000 AFECON Analog configuration 0x00080000 Rev. B | Page 54 of 312...

  • Page 55: Register Details: Analog Die Circuitry

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: ANALOG DIE CIRCUITRY AFE CONFIGURATION REGISTER Address: 0x400C2000, Reset: 0x00080000, Name: AFECON Specific bits in this registers are relevant to particular blocks in the analog die. The relevant bits for each block are as follows: ...
  • Page 56 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access EXBUFEN Enable Excitation Buffer on High Speed DAC Output. High speed DAC excitation buffer disabled. High speed DAC excitation buffer enabled. ADCCONVEN ADC Conversion Start Enable. ADC idle. ADC powered on but not converting.

  • Page 57: Adc Circuit

    ADuCM355 Hardware Reference Manual UG-1262 ADC CIRCUIT ADC CIRCUIT OVERVIEW The SAR ADC circuit is implemented on the analog die. The die operates from a 2.8 V to 3.6 V power supply. The Arm Cortex-M3 processor interfaces to the ADC via an internal die-to-die interface. The ADC uses a precision, low drift, factory calibrated 1.82 V reference.

  • Page 58: Adc Circuit Operation

    UG-1262 ADuCM355 Hardware Reference Manual  One high speed current input channel for performing impedance measurements up to 200 kHz. This channel has dedicated TIAs with a programmable gain resistor.  Multiple external voltage inputs.  Eight dedicated voltage input channels, AIN0 to AIN7.

  • Page 59: Adc Low Power Current Input Channels

    ADuCM355 Hardware Reference Manual UG-1262 FFFF C000 8000 4000 0000 0.2V 1.11V 2.02V Figure 9. Ideal ADC Transfer Function, Voltage Input to ADC vs. Output Codes, Where Input is ADCVBIAS_CAP at 1.11 V To calculate the input voltage (V ), use the following equation to convert ADC codes to a voltage: For PGA gain = 1, = (VREF ×...

  • Page 60: Adc Input Circuit

    UG-1262 ADuCM355 Hardware Reference Manual The low power TIA outputs have a low-pass filter. The resistor connecting the TIA output to the input mux is typically 1 MΩ with a recommended external low-pass filter capacity of 4.7 μF resulting in a very low cutoff frequency. This resistor is labeled RFILTER in Figure 10.

  • Page 61: Averaging, Statistics, And Outlier Detection Options

    ADuCM355 Hardware Reference Manual UG-1262 When changing ADC input channels, restarting the ADC, or changing the ADC update rates via the ADCFILTERCON register, reset the sinc2 filter. If the sinc2 filter is not reset, the ADC samples with the new settings are inaccurate.

  • Page 62: Internal Temperature Sensor Channels

    UG-1262 ADuCM355 Hardware Reference Manual INTERNAL TEMPERATURE SENSOR CHANNELS ADuCM355 analog die contains two internal temperature sensor channels. Temperature Sensor 0 The temperature sensor outputs a voltage proportional to die temperature. This voltage is linear relative to temperature. This internal channel is measured via the ADC by selecting the temperature sensor channels as the positive and negative inputs from the mux.

  • Page 63: Adc Initialization

    ADuCM355 Hardware Reference Manual UG-1262 BITM_AFE_ADCINTSTA_TEMPRDY; // Clear interrupt flag void CalculateTemp(void) // PGA GAIN of 1.5x assumed fTemp = (float)(( TEMP_RESULT/(1.5*8.13))-273.15); // ((Temperature reading/(PGA_Gain*8.13)-273.15 Temperature Sensor 1 A second backup temperature sensor is provided on the ADuCM355 analog die for functional safety purposes. Only use Temperature Sensor 1 to crosscheck the Temperature Sensor 0 channel.

  • Page 64: Adc Calibration

    ADC CALIBRATION Because of the multiple input types of the ADuCM355, there are multiple offset and gain calibration options. The ADC must be recalibrated when switching from low power mode to high power mode, regardless of the gain change. For optimal performance, calibrate the ADC in low power mode and high power mode, if both power modes are used.

  • Page 65: Adc Digital Signal Processor (Dsp) Built In Self Test

    UG-1262 When calibrating the gain error for the ADC voltage channels during Analog Devices production testing, the value loaded to the ADCGAINGN1P5 calibration register is ≥0x4000. To ensure this value, the target ADC result is higher than normal. The factory trim value for the ADC reference is 1.82 V, but for calibration purposes, the target voltage is 1.835 V.

  • Page 66: Voltage Reference Options

    UG-1262 ADuCM355 Hardware Reference Manual VOLTAGE REFERENCE OPTIONS The ADC features internal 1.82 V and 2.5 V voltage reference sources, as shown in Figure 14. AVDD 1.82V FOR VREF_OUT HIGH POWER DAC AIN3/ BUFFER BUF_VREF1V8 1.82V 1.82V ANALOG REFERENCE BUFSENCON[8]...

  • Page 67: Register Summary: Adc Circuit

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: ADC CIRCUIT Table 58. ADC Control Register Summary Address Name Description Reset Access 0x400C21A8 ADCCON ADC configuration register 0x00000000 0x400C2044 ADCFILTERCON ADC output filters configuration 0x00000301 0x400C2074 ADCDAT Raw result 0x00000000 0x400C2078 DFTREAL...
  • Page 68 UG-1262 ADuCM355 Hardware Reference Manual Table 62. ADC Digital Logic Test Register Summary (Optional) Address Name Description Reset Access 0x400C0434 MKEY Key access for DSPUPDATEEN register 0x00000000 0x400C0438 DSPUPDATEEN Digital logic test enable 0x00000000 0x400C2374 TEMPCON1 Temperature Sensor 1 control 0x00020000 Rev.

  • Page 69: Register Details: Adc Circuit

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: ADC CIRCUIT ADC CONFIGURATION REGISTER Address: 0x400C21A8, Reset: 0x00000000, Name: ADCCON Table 63. Bit Descriptions for ADCCON Bits Bit Name Settings Description Reset Access [31:19] Reserved Reserved. [18:16] GNPGA PGA Gain Setup. Gain = 1.

  • Page 70: Adc Output Filters Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access 01010 AVDD_REG/2. 01011 Temperature Sensor 0 positive input. 01100 ADCVBIAS_CAP. 01101 DE0. 01110 SE0. 01111 SE1. 010000 VREF_2.5V/2. Low power 2.5 V reference divided by 2. 010001 Reserved.

  • Page 71: Raw Result Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access [11:8] SINC2OSR Sinc2 Filter Oversampling Rates. 22 samples for this OSR setting. 44 samples for this OSR setting. 89 samples for this OSR setting. 178 samples for this OSR setting.

  • Page 72: Dft Result, Imaginary Part Register

    UG-1262 ADuCM355 Hardware Reference Manual DFT RESULT, IMAGINARY PART REGISTER Address: 0x400C207C, Reset: 0x00000000, Name: DFTIMAG Table 67. Bit Descriptions for DFTIMAG Bits Bit Name Settings Description Reset Access [31:18] Reserved Reserved. [17:0] DATA DFT Imaginary. DFT hardware accelerator returns a complex number. This register returns the 18-bit imaginary part of the complex number from the DFT result.

  • Page 73: Analog Capture Interrupt Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access SINC2RDYIEN Low-Pass Filter Result Interrupt. Supply rejection filter result ready for interrupt enable. The SINC2DAT register is ready for reading. Interrupt disabled. Interrupt enabled. DFTRDYIEN DFT Result Ready Interrupt. The DFTREAL and DFTIMAG registers are ready for reading.

  • Page 74: Afe Dsp Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access SINC2RDY Low-Pass Filter Result Status. Supply rejection filter result ready interrupt. R/W1C User must write 1 to this bit to clear it. Writing 0 has no effect. Interrupt not asserted.

  • Page 75: Temperature Sensor 0 Configuration Register

    ADuCM355 Hardware Reference Manual UG-1262 TEMPERATURE SENSOR 0 CONFIGURATION REGISTER Address: 0x400C2174, Reset: 0x00000000, Name: TEMPCON0 Table 73. Bit Descriptions for TEMPCON0 Bits Bit Name Settings Description Reset Access [31:4] Reserved Reserved. [3:2] CHOPFRESEL Chop Mode Frequency Setting. Sets frequency of chop mode switching.

  • Page 76: Number Of Repeat Adc Conversions Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access V1P8HPADCILIMITEN High Power ADC Input Current Limit. Protects ADC input buffer. Disable buffer current limit. Enable buffer current limit. Recommended setting. V1P8HPADCEN High Power 1.8 V Reference Buffer. Enable for normal ADC conversions.

  • Page 77: Offset Calibration Lptia0 Channel Register

    ADuCM355 Hardware Reference Manual UG-1262 OFFSET CALIBRATION LOW POWER TIA0 CHANNEL REGISTER Address: 0x400C2288, Reset: 0x00000000, Name: ADCOFFSETLPTIA0 Table 78. Bit Descriptions for ADCOFFSETLPTIA0 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Offset Calibration for Low Power TIA0. Represented as a twos complement number.

  • Page 78: Offset Calibration High Speed Tia Channel Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access 0x4001 1.000061 (minimum positive gain adjustment). 0x4000 1.0. ADC result multiplied by 1. No gain adjustment. Default value. 0x3FFF 0.999939 (minimum negative gain adjustment). 0x2000 0.5. ADC result multiplied by 0.5.

  • Page 79: Gain Calibration Voltage Input Channel (Pga Gain = 1) Register

    ADuCM355 Hardware Reference Manual UG-1262 GAIN CALIBRATION VOLTAGE INPUT CHANNEL (PGA GAIN = 1) REGISTER Address: 0x400C2240, Reset: 0x00004000, Name: ADCGAINGN1 Table 85. Bit Descriptions for ADCGAINGN1 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. Gain Calibration PGA Gain 1. ADC gain correction for voltage input channels.

  • Page 80: Offset Calibration Voltage Input Channel (Pga Gain = 2) Register

    UG-1262 ADuCM355 Hardware Reference Manual OFFSET CALIBRATION VOLTAGE INPUT CHANNEL (PGA GAIN = 2) REGISTER Address: 0x400C22C8, Reset: 0x00000000, Name: ADCOFFSETGN2 Table 88. Bit Descriptions for ADCOFFSETGN2 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Offset Calibration Voltage Channel Gain 2. ADC offset correction for inputs using PGA gain = 2, represented as a twos complement number.

  • Page 81: Gain Calibration Voltage Input Channel (Pga Gain = 4) Register

    ADuCM355 Hardware Reference Manual UG-1262 GAIN CALIBRATION VOLTAGE INPUT CHANNEL (PGA GAIN = 4) REGISTER Address: 0x400C2278, Reset: 0x00004000, Name: ADCGAINGN4 Table 91. Bit Descriptions for ADCGAINGN4 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Gain Calibration PGA Gain 4. ADC gain correction for voltage input channels.

  • Page 82: Offset Calibration Temperature Sensor Channel 0 Register

    UG-1262 ADuCM355 Hardware Reference Manual OFFSET CALIBRATION TEMPERATURE SENSOR CHANNEL 0 REGISTER Address: 0x400C223C, Reset: 0x00000000, Name: ADCOFFSETTEMPSENS0 Table 94. Bit Descriptions for ADCOFFSETTEMPSENS0 Bits Bit Name Settings Description Reset Access [31:15] Reserved Reserved. [14:0] VALUE Offset Calibration Temperature Sensor. ADC offset correction for temperature sensor channel, represented as a twos complement number.

  • Page 83: Maximum Value Check Register

    ADuCM355 Hardware Reference Manual UG-1262 MAXIMUM VALUE CHECK REGISTER Address: 0x400C20B0, Reset: 0x00000000, Name: ADCMAX Table 98. Bit Descriptions for ADCMAX Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:0] MAXVAL ADC Maximum Threshold. Optional maximum ADCDAT threshold. If a value greater than ADCMAX is measured by the ADC, ADCINTSTA, Bit 5 is set to 1.

  • Page 84: Mean Output Register

    UG-1262 ADuCM355 Hardware Reference Manual MEAN OUTPUT REGISTER Address: 0x400C21C8, Reset: 0x00000000, Name: STATSMEAN Table 102. Bit Descriptions for STATSMEAN Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:0] MEAN Mean Output. Mean value calculated for the number of ADC samples set by STATSCON, Bits[6:4].

  • Page 85: Low Power Potentiostat Amplifiers And Low Power Tias

    LOW POWER TIAs Two low power TIA channels are available on the ADuCM355. The load resistor and gain resistor values are specified in the Lx registers. Select the TIA gain resistor that maximizes the ADC input voltage range for the selected PGA gain setting. For example, if the PGA gain setting is 1, select a TIA gain resistor to maximize the ±900 mV range.
  • Page 86 UG-1262 ADuCM355 Hardware Reference Manual Close SW0 when changing the R value, and open SW0 again when the change is complete. If high currents are detected on the low power TIA input path when using an oxygen electrochemical sensor, close the shorting switch, SW1, to protect the low power TIA input circuitry.
  • Page 87 ADuCM355 Hardware Reference Manual UG-1262 VBIAS1 VZERO1 VREF_2.5V AIN7_LPF1 LPDACSW1[3] LPDACSW1[1] SW12 SW13 LPBUF OPEN: LPDACCON1[5] = 1 LPDACCON1[3] SW15 AND LPDACSW1[4] = 0 12-BIT LPDAC1 VZERO1 – 6-BIT LPREF LPDACCON1[4] CAP_POT1 SW10 10kΩ 10kΩ SW11 LOAD LPTIA – LPTIACON1...

  • Page 88: Low Power Dacs

    UG-1262 ADuCM355 Hardware Reference Manual Figure 18 shows the relationship between the R and R settings for the low power TIA. R is configured by setting LPTIACON0, LOAD GAIN LOAD Bits[12:10]. R is configured by LPTIACON0, Bits[9:5]. When R is large, it uses resistors from the R...
  • Page 89 ADuCM355 Hardware Reference Manual UG-1262 LOW POWER DAC BLOCK DIAGRAM MAIN DAC VREF_2.5V 2.4V TO TOP MUX TO BOTTOM MUX 2.36615V TO TOP MUX SubDAC 63 × R1 TO BOTTOM MUX SET BY LPDACDATx[5:0] TO TOP MUX 62 × R1 TO BOTTOM MUX 63 ×...
  • Page 90 UG-1262 ADuCM355 Hardware Reference Manual To control the switches individually, use the LPDACSWx registers. LPDACSWx, Bit 5 must be set to 1 so that each switch can be individually controlled via LPDACSWx, Bits[4:0]. Relationship Between 12-Bit and 6-Bit Outputs, Hardware Compensation Enabled The 12-bit and 6-bit outputs are mostly independent.
  • Page 91 ADuCM355 Hardware Reference Manual UG-1262 Table 106. Recommended Switch Settings in Low Power Potentiostat Loop LPDACCONx LPDACSWx LPTIASWx Measurement Name Bit 5 Setting Bits[5:0] Setting Bits[13:0] Setting Description Amperometric Mode 0xXX (don’t care) 0x302C or 0b11 Normal dc current measurement. External...

  • Page 92: Register Summary: Low Power Tia/Potentiostat And Dac Circuits

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS Table 107. Low Power Potentiostat and TIA Control Register Summary Address Name Description Reset Access 0x400C20EC LPTIACON0 Low power TIA control bits Channel 0 0x00000003 0x400C20E4 LPTIASW0...

  • Page 93: Register Details: Low Power Tia/Potentiostat And Dac Circuits

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS LOW POWER TIA CONTROL BITS CHANNEL 0 REGISTER Address: 0x400C20EC, Reset: 0x00000003, Name: LPTIACON0 Table 109. Bit Descriptions for LPTIACON0 Bits Bit Name Settings Description Reset Access...

  • Page 94: Low Power Tia Switch Configuration For Channel 0 Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access 10101 120 kΩ. R gain = 120 kΩ − (R − 100 Ω). LOAD 10110 128 kΩ. R gain = 128 kΩ − (R − 100 Ω). LOAD 10111 160 kΩ.

  • Page 95: Low Power Tia Control Bits Channel 1 Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access SW9 Switch Control Active High. Open switch. Close switch. SW8 Switch Control Active High. Open switch. Close switch. SW7 Switch Control Active High. Open switch. Close switch. SW6 Switch Control Active High.
  • Page 96 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [12:10] TIARL Set R LOAD 0 Ω. 10 Ω. 30 Ω. 50 Ω. 100 Ω. 1.6 kΩ. R must be ≥2 kΩ. 3.1 kΩ. R must be ≥4 kΩ.

  • Page 97: Low Power Tia Switch Configuration For Channel 1 Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access PAPDEN Potentiostat Amplifier Power-Down. Low power Potentiostat Amplifier 1 power-down control bit. Power-up. Power-down. TIAPDEN TIA Power-Down. Low power TIA1 power-down control bit. Power up. Power down. LOW POWER TIA SWITCH CONFIGURATION FOR CHANNEL 1 REGISTER Address: 0x400C20E0, Reset: 0x00000000, Name: LPTIASW1 See Figure 17 for details on the switches mentioned in this register.

  • Page 98: Lpdac0 Data Out Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access SW2 Switch Control Active High. Open switch. Close switch. SW1 Switch Control Active High. Open switch. Close switch. SW0 Switch Control Active High. Open switch. Close switch. LPDAC0 DATA OUT REGISTER Address: 0x400C2120, Reset: 0x00000000, Name: LPDACDAT0 Table 113.

  • Page 99: Lpdac0 Control Register

    ADuCM355 Hardware Reference Manual UG-1262 LPDAC0 CONTROL REGISTER Address: 0x400C2128, Reset: 0x00000002, Name: LPDACCON0 Table 115. Bit Descriptions for LPDACCON0 Bits Bit Name Settings Description Reset Access [31:7] Reserved Reserved. WAVETYPE Low Power DAC Source. Direct from the LPDACDAT0 register.

  • Page 100: Lpdac1 Switch Control Register

    UG-1262 ADuCM355 Hardware Reference Manual LPDAC1 SWITCH CONTROL REGISTER Address: 0x400C2130, Reset: 0x00000000, Name: LPDACSW1 Table 117. Bit Descriptions for LPDACSW1 Bits Bit Name Settings Description Reset Access [31:6] Reserved Reserved. LPMODEDIS Switch Control. Controls switches connected to the output of LPDAC1.

  • Page 101: Low Power Reference Control Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access PWDEN Low Power DAC1 Power. Power-down control bit for low power DAC1. Low Power DAC1 powered on. Clear to 0 to power on low power DAC1. Low Power DAC1 powered off. Default. Power down low power DAC1 and open all switches on the low power DAC1 output.

  • Page 102: High Speed Tia Circuits

    UG-1262 ADuCM355 Hardware Reference Manual HIGH SPEED TIA CIRCUITS The high speed TIA is intended for measuring wide bandwidth input signals up to 200 kHz. The output of the high speed TIA transfers to the main ADC mux, where the high speed TIA can be selected as the ADC input channel. The high speed TIA is especially designed for impedance measurements in conjunction with the high speed DAC and excitation amplifier.
  • Page 103 ADuCM355 Hardware Reference Manual UG-1262 DE0RESCON, Bits[7:0] (DE0) and DE1RESCON, Bits[7:0] (DE1) Setting and R Value (Ω) and R Value LOAD03 LOAD05 TIA2_03 TIA2_05 0x7A 40.07 kΩ 0x82 80.07 kΩ 0x8A 160.07 kΩ 0x1B 50 Ω 0x33 100 Ω 0x4B 190 Ω...

  • Page 104: Using De0 And De1 Inputs With The High Speed Tia

    UG-1262 ADuCM355 Hardware Reference Manual USING DE0 AND DE1 INPUTS WITH THE HIGH SPEED TIA To use DE0 as the input of the high speed TIA, set the following register values:  DE0RESCON = value required to set R and R .

  • Page 105: Register Summary: High Speed Tia Circuits

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: HIGH SPEED TIA CIRCUITS AFECON, Bit 11 and AFECON, Bit 5 are relevant to the high speed TIA block. See Table 52 for more details. Table 121. High Speed TIA Circuit Register Summary...

  • Page 106: Register Details: High Speed Tia Circuits

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: HIGH SPEED TIA CIRCUITS HIGH SPEED R CONFIGURATION REGISTER Address: 0x400C20F0, Reset: 0x0000000F, Name: HSRTIACON This register controls the high speed TIA R , current protection diode, and feedback capacitor. Table 122. Bit Descriptions for HSRTIACON...

  • Page 107: De0 High Speed Tia Resistor Configuration Register

    ADuCM355 Hardware Reference Manual UG-1262 DE0 HIGH SPEED TIA RESISTOR CONFIGURATION REGISTER Address: 0x400C20F8, Reset: 0x000000FF, Name: DE0RESCON Table 124. Bit Descriptions for DE0RESCON Bits Bit Name Settings Description Reset Access [31:8] Reserved Reserved. [7:0] DE0RCON DE0 R and R Setting.

  • Page 108: High Speed Dac Circuits

    UG-1262 ADuCM355 Hardware Reference Manual HIGH SPEED DAC CIRCUITS The 12-bit high speed DAC generates an ac excitation signal when measuring the impedance of an external sensor. The DAC output signal can be controlled directly by writing to a data register or by the automated waveform generator block. The high speed DAC signal is fed to an excitation amplifier designed specifically to couple the ac signal on top of the normal dc bias voltage of the sensor.

  • Page 109: Recommended Configuration In Hibernate Mode

    ADuCM355 Hardware Reference Manual UG-1262  Ensure CLKSEL, Bits[1:0] selects a 32 MHz clock source. For example, an internal high speed oscillator is selected if CLKSEL, Bits[1:0] = 00. Ensure that the system clock divide ratio is 1 (CLKCON0, Bits[5:0] = 0 or 1).

  • Page 110: Avoiding Incoherency Errors Between Excitation And Measurement Frequencies During Impedance Measurements

    UG-1262 ADuCM355 Hardware Reference Manual OPEN THIS SWITCH VREF_2.5V TO DISCONNECT POTENTIOSTAT AMP – DACN 2.4V BIAS = 80kHz – DACP DUAL VBIAS0 OUTPUTS 12-BIT 12-BIT VDAC WAVE SW12 ZERO C = ~0.1µF DACN 0.2V C = 0.1µF DAC TO DAC BUFFERS –...
  • Page 111 ADuCM355 Hardware Reference Manual UG-1262 The high speed DAC transfer function is shown in Figure 25. Note that in Figure 26 the common-mode voltage setting for the calibration circuit is set by the noninverting input of the high speed TIA.

  • Page 112: Register Summary: High Speed Dac Circuits

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: HIGH SPEED DAC CIRCUITS Table 128. High Speed DAC Control Register Summary Address Name Description Reset Access 0x400C2010 HSDACCON High speed DAC configuration 0x0000001E 0x400C2048 HSDACDAT Direct write to DAC output control value...

  • Page 113: Register Details: High Speed Dac Circuits

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: HIGH SPEED DAC CIRCUITS HIGH SPEED DAC CONFIGURATION REGISTER Address: 0x400C2010, Reset: 0x0000001E, Name: HSDACCON Table 130. Bit Descriptions for HSDACCON Bits Bit Name Settings Description Reset Access [31:13] Reserved Reserved. INAMPGNMDE Excitation Amplifier Gain Control. Selects the gain of excitation amplifier.

  • Page 114: Dac Gain Register

    UG-1262 ADuCM355 Hardware Reference Manual DAC GAIN REGISTER Address: 0x400C2260, Reset: 0x00000800, Name: DACGAIN Protected by CALDATLOCK. Valid for all settings of HSDACCON Bit 12 and HSDACCON Bit 0. Table 133. Bit Descriptions for DACGAIN Bits Bit Name Settings Description...

  • Page 115: Dac Offset With Attenuator Enabled (High Power Mode) Register

    Access [31:5] Reserved Reserved. DACGAINCAL DAC Gain Enable. Use the DAC gain calculated during the Analog Devices factory trim and stored in the DACGAIN register. Bypass DAC gain correction. Enable DAC gain correction using value in the DACGAIN register. DACOFFSETCAL Bypass DAC Offset.

  • Page 116: Waveform Generator For Sinusoid Frequency Control Word Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [2:1] TYPESEL Selects the Type of Waveform. Direct write to DAC. User code writes to the HSDACDAT register directly. Sinusoid. Set AFECON, Bit 4 to 1, set this bit to 10, and the DAC outputs a sine wave.

  • Page 117: Programmable Switches Connecting The External Sensor To The High Speed Dac And High Speed Tia

    ADuCM355 Hardware Reference Manual UG-1262 PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH SPEED DAC AND HIGH SPEED TIA ADuCM355 provides flexibility for connecting external pins to the high speed DAC excitation amplifier and to the high speed TIA inverting input.
  • Page 118 UG-1262 ADuCM355 Hardware Reference Manual EXCITATION BUFFER AMPLIFIER LOOP Dx SWITCHES DSWFULLCON OR SWCON[3:0] RCAL0 RCAL1 Px SWITCHES PSWFULLCON OR SWCON[7:4] DVDD_REG_AD LOAD02 Nx SWITCHES NSWFULLCON OR SWCON[11:8] LOAD04 TSWFULLCON OR SWCON[15:12] HSTIACON[1:0] HIGH SPEED SELECTS SOURCE Tx SWITCHES TRANSIMPEDANCE...
  • Page 119 ADuCM355 Hardware Reference Manual UG-1262 There are two options to control the programmable switches to the high speed DAC excitation amplifier and the high speed TIA inverting input: SWCON, Bit 16 = 0 and SWCON, Bit 16 =1. For SWCON, Bit 16 = 0, the bit selects the SWCON register as the control source for these switches. The Tx, Nx, Px, and Dx switches are controlled in groups as follows: ...

  • Page 120: Register Summary: Programmable Switches

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: PROGRAMMABLE SWITCHES The status of all the switches can be read from the switch status registers at any time. These statuses indicate whether each switch is open or closed. The switch status registers are DSWSTA, PSWSTA, NSWSTA, and TSWSTA.

  • Page 121: Register Details: Programmable Switches

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: PROGRAMMABLE SWITCHES SWITCH MATRIX CONFIGURATION REGISTER Address: 0x400C200C, Reset: 0x0000FFFF, Name: SWCON Table 144. Bit Descriptions for SWCON Bits Bit Name Settings Description Reset Access [31:20] Reserved Reserved. T11CON Control of T11 Switch.

  • Page 122: Dx Switch Matrix Full Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access 0111 P7 closed, others open. 1000 P8 closed, others open. 1001 P9 closed, others open. 1010 P10 closed, others open. 1011 P11 closed, others open. 1100 P12 closed, others open.

  • Page 123: Nx Switch Matrix Full Configuration Register

    ADuCM355 Hardware Reference Manual UG-1262 Nx SWITCH MATRIX FULL CONFIGURATION REGISTER Address: 0x400C2154, Reset: 0x00000000, Name: NSWFULLCON This register allows individual control of the Nx switches. The bit names are the same as the switch names shown in Figure 27.

  • Page 124: Px Switch Matrix Full Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual Px SWITCH MATRIX FULL CONFIGURATION REGISTER Address: 0x400C2158, Reset: 0x00000000, Name: PSWFULLCON This register allows individual control of the Px switches. The bit names are the same as the switch names shown in Figure 27.

  • Page 125: Tx Switch Matrix Full Configuration Register

    ADuCM355 Hardware Reference Manual UG-1262 Tx SWITCH MATRIX FULL CONFIGURATION REGISTER Address: 0x400C215C, Reset: 0x00000000, Name: TSWFULLCON This register allows individual control of the Tx switches. The bit names are the same as the switch names shown in Figure 27.

  • Page 126: Dx Switch Matrix Status Register

    UG-1262 ADuCM355 Hardware Reference Manual Dx SWITCH MATRIX STATUS REGISTER Address: 0x400C21B0, Reset: 0x00000000, Name: DSWSTA This gives the status of the Dx switches shown in Figure 27. Table 149. Bit Descriptions for DSWSTA Bits Bit Name Settings Description Reset...

  • Page 127: Nx Switch Matrix Status Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access P11STA Status of P11 Switch. Switch open. Switch closed. P10STA Status of P10 Switch. Switch open. Switch closed. P9STA Status of P9 Switch. Switch open. Switch closed. P8STA Status of P8 Switch.

  • Page 128: Tx Switch Matrix Status Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access N8STA Status of N8 Switch. Switch open. Switch closed. N7STA Status of N7 Switch. Switch open. Switch closed. N6STA Status of N6 Switch. Switch open. Switch closed. N5STA Status of N5 Switch.
  • Page 129 ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access T5STA Status of T5 Switch. Switch open. Switch closed. T4STA Status of T4 Switch. Switch open. Switch closed. T3STA Status of T3 Switch. Switch open. Switch closed. T2STA Status of T2 Switch.

  • Page 130: Sequencer

    DSP blocks. The sequencer handles timing critical operations without being subject to system load. Four command sequences are supported by hardware on the ADuCM355. These sequences can be stored in the SRAM to switch between different measurement procedures. Only one sequence can be executed by the sequencer at a time. However, the user can configure which sequences the sequencer executes and the order in which they are executed.

  • Page 131: Sequencer Operation

    ADuCM355 Hardware Reference Manual UG-1262 For example, when writing to the WGCON register directly through the die to die interface, Address 0x400C2014 is used. To write to the same register using the sequencer, the address field must be 0b0000101 (Bits[8:2] of the address used by the external controller).
  • Page 132 UG-1262 ADuCM355 Hardware Reference Manual RUN SEQUENCE ENABLE/DISABLE LOAD TRIM VALUES ANALOG BLOCKS, START ADC CONVERSION, STORE RESULTS IN SRAM BOOT MEASUREMENT MEASUREMENT INITIALIZATION HIBERNATE HIBERNATE • • • LOAD SEQUENCES TO SRAM, HIBERNATE MODE WITH SETUP SEQUENCE, FIFO, SLEEP AND SRAM CONTENTS WAKE-UP TIMER, AND GPIOs.
  • Page 133 ADuCM355 Hardware Reference Manual UG-1262 The interrupt flags associated with the data FIFO include empty, full, overflow, underflow, and threshold. These interrupts are user readable using the INTCFLAGx registers (see the AFE Interrupts section for more details). Each flag has an associated maskable interrupt.

  • Page 134: Sequencer And Fifo Registers

    UG-1262 ADuCM355 Hardware Reference Manual SEQUENCER AND FIFO REGISTERS Table 154. Sequence and FIFO Registers Summary Address Name Description Reset Access 0x400C2004 SEQCON Sequencer configuration register 0x00000002 0x400C2008 FIFOCON FIFO configuration register 0x00001010 0x400C2060 SEQCRC Sequencer CRC value register 0x00000001...
  • Page 135 ADuCM355 Hardware Reference Manual UG-1262 FIFO Configuration Register Address: 0x400C2008, Reset: 0x00001010, Name: FIFOCON Table 156. Bit Descriptions for FIFOCON Register Bits Bit Name Settings Description Reset Access [31:16] RESERVED Reserved. [15:13] DATAFIFOSRCSEL Data FIFO Source Select. 000, 001, ADC data. The ADC data is the output of the sinc3 filter.
  • Page 136 UG-1262 ADuCM355 Hardware Reference Manual Data FIFO Read Register Address: 0x400C206C, Reset: 0x00000000, Name: DATAFIFORD Table 160. Bit Descriptions for DATAFIFORD Register Bits Bit Name Description Reset Access [31:0] DATAFIFOOUT Data FIFO Read. When the data FIFO is empty, a read of this register returns 0x00000000. See Figure 32 and Figure 33 for word format details.
  • Page 137 ADuCM355 Hardware Reference Manual UG-1262 Sequence 2 Information Register Address: 0x400C21D0, Reset: 0x00000000, Name: SEQ2INFO Table 165. Bit Descriptions for SEQ2INFO Register Bits Bit Name Description Reset Access [31:27] Reserved Reserved. [26:16] SEQ2INSTNUM SEQ2 Instruction Number. [15:11] Reserved Reserved. [10:0] SEQ2STARTADDR SEQ2 Start Address.
  • Page 138 UG-1262 ADuCM355 Hardware Reference Manual Sequence 3 Information Register Address: 0x400C21E4, Reset: 0x00000000, Name: SEQ3INFO Table 169. Bit Descriptions for SEQ3INFO Register Bits Bit Name Description Reset Access [31:27] Reserved Reserved. [26:16] INSTNUM SEQ3 Instruction Number. [15:11] Reserved Reserved. [10:0] STARTADDR SEQ3 Start Address.

  • Page 139: Afe Interrupts

    AFE INTERRUPTS There are interrupt options available on the ADUCM355 analog front end that can be configured to toggle the internal GPIO pin on the digital die. The GPIO pin is connected internally and is not bonded out of the LGA package.

  • Page 140: Interrupt Registers

    UG-1262 ADuCM355 Hardware Reference Manual INTERRUPT REGISTERS Table 174. Interrupt Registers Summary Address Name Description Reset Access 0x400C3000 INTCPOL Interrupt polarity register 0x00000000 0x400C3004 INTCCLR Interrupt clear register 0x00000000 0x400C3008 INTCSEL0 Interrupt controller select register 0x00002000 0x400C300C INTCSEL1 Interrupt controller select register...
  • Page 141 ADuCM355 Hardware Reference Manual UG-1262 Interrupt Controller Select Registers Address 0x400C3008, Reset: 0x00002000, Name: INTCSEL0 Address 0x400C300C, Reset: 0x00002000, Name: INTCSEL1 Table 177. Bit Descriptions for INTCSEL0 and INTCSEL1 Registers Bits Bit Name Settings Description Reset Access INTSEL31 Attempt to Break IRQ Enable.
  • Page 142 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access INTSEL9 Custom Interrupt 0 Enable. Interrupt disabled. Interrupt enabled. Reserved Reserved. INTSEL7 Mean IRQ Enable. Interrupt disabled. Interrupt enabled. INTSEL6 ADC Delta Fail IRQ Enable. Interrupt disabled. Interrupt enabled.
  • Page 143 ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access FLAG25 Data FIFO Threshold IRQ Status. Interrupt not asserted. Interrupt asserted. FLAG24 Data FIFO Empty IRQ Status. Interrupt not asserted. Interrupt asserted. FLAG23 Data FIFO Full IRQ Status.
  • Page 144 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access FLAG4 ADC Minimum Fail IRQ Status. When this bit is set, it indicates that an ADC result is below the minimum value as specified by the ADCMIN register. If this bit is clear, it indicates that no ADC value below the limit is detected since the last time this bit was cleared.

  • Page 145: Sleep And Wake-Up Timer

    SLEEP AND WAKE-UP TIMER FEATURES The ADuCM355 integrates a 20-bit sleep and wake-up timer. The sleep and wake-up timer provides automated control of the sequencer and can run up to eight sequences sequentially in any order from SEQ0 to SEQ3. Each sequence has a defined sleep period (SEQxSLEEPx) and a defined active period (SEQxWUPx).

  • Page 146: Recommended Sleep And Wake-Up Timer Operation

    The timer loads the values from the SEQxSLEEPH and SEQxSLEEPL registers and begins counting down again when the sequencer is running. When the timer elapses, the ADuCM355 returns to sleep mode if the TMRCON register, Bit 0 = 1. If the AFE PWRMOD register, Bit 3 = 1, the ADuCM355 returns to sleep mode at the end of the last sequence.
  • Page 147 ADuCM355 Hardware Reference Manual UG-1262 Timer Control Register Address 0x400C0800, Reset: 0x0000, Name: CON The CON register is the wake-up timer control register. Table 181. Bit Descriptions for CON Register Bits Bit Name Settings Description Reset Access [15:7] Reserved Reserved.
  • Page 148 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [7:6] SEQD Sequence D Configuration. These bits select SEQ0, SEQ1, SEQ2, or SEQ3 for Timer Sequence D. Fills in SEQ0. Fills in SEQ1. Fills in SEQ2. Fills in SEQ3.
  • Page 149 ADuCM355 Hardware Reference Manual UG-1262 Sequence 0 to Sequence 3 Sleep Time Registers (LSB) Address 0x400C0810, Reset: 0xFFFF, Name: SEQ0SLEEPL Address 0x400C0820, Reset: 0xFFFF, Name: SEQ1SLEEPL Address 0x400C0830, Reset: 0xFFFF, Name: SEQ2SLEEPL Address 0x400C0840, Reset: 0xFFFF, Name: SEQ3SLEEPL The SEQxSLEEPL registers define the device active time for SEQ0 to SEQ3. The counter is 20 bits. These registers set the 16 LSBs.

  • Page 150: Use Case Configurations

    UG-1262 ADuCM355 Hardware Reference Manual USE CASE CONFIGURATIONS ADuCM355 is primarily designed for controlling and measuring electrochemical sensors. This section gives suggested setup details for the main use cases of the ADuCM355 with an electrochemical sensor. HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR In this mode, the digital die and analog die are in hibernate mode.
  • Page 151 ADuCM355 Hardware Reference Manual UG-1262 EXCITATION BUFFER AMPLIFIER LOOP Dx SWITCHES DSWFULLCON OR SWCON[3:0] RCAL0 RCAL1 Px SWITCHES PSWFULLCON OR SWCON[7:4] DVDD_REG_AD LOAD02 Nx SWITCHES NSWFULLCON OR SWCON[11:8] LOAD04 TSWFULLCON OR SWCON[15:12] HSTIACON[1:0] HIGH SPEED SELECTS SOURCE Tx SWITCHES TRANSIMPEDANCE...

  • Page 152: Measuring A Dc Current Output

    UG-1262 ADuCM355 Hardware Reference Manual MEASURING A DC CURRENT OUTPUT When measuring a dc current output, the ADC is powered on and set to measure the low power TIA input channel. The user has the option to average the ADC results before reading to the digital die, or to use DMA mode to directly move the ADC results to the digital die SRAM.

  • Page 153: Pulse Test (Chronoamperometry)

    ADuCM355 Hardware Reference Manual UG-1262 VBIAS0 VZERO0 VREF_2.5V AIN4_LPF0 VZERO1 CHANNEL 0 SW15 SW12 SW13 LPBUF LP DUAL OUTPUT AMP 0 – SW14 LPREF SW10 CAP_POT0 10kΩ 10kΩ SW11 LPTIA0 RL[2:0] – LOAD RF[2:0] GAIN[4:0] RC0_0 RC00 RC0_1 SW[0:15] CORRESPONDING TO LPTIASW[0:15]...

  • Page 154: Cyclic Voltammetry

    UG-1262 ADuCM355 Hardware Reference Manual pADI_AFE->TSWFULLCON = 0x110; // Step 2: Close T9 & T5. Leave T10, T11 open pADI_AFE->SWCON |= BITM_AFE_SWCON_SWSOURCESEL; // Step 3: to write to T-Switch control register AfeHSTIACon(AMPPOWER_NORM, HSTIABIAS_VZERO0); // Set common-mode source as Vzero0 if HSTIA...
  • Page 155 ADuCM355 Hardware Reference Manual UG-1262 VBIAS0 VZERO0 VREF_2.5V AIN4_LPF0 LPDACSW0[3] LPDACSW0[1] SW12 SW13 ULPBUF OPEN: LPDACCON0[5] = 1 LPDACCON0[3] SW15 AND LPDACSW0[4] = 0 12-BIT LPDAC0 VZERO0 – 6-BIT ULPREF LPDACCON0[4] CAP_POT0 SW14 LPDACSW0[2] SW10 TO CHANNEL 1 10kΩ 10kΩ...
  • Page 156 UG-1262 ADuCM355 Hardware Reference Manual EXCITATION BUFFER AMPLIFIER LOOP Dx SWITCHES DSWFULLCON OR SWCON[3:0] RCAL0 RCAL1 Px SWITCHES PSWFULLCON OR SWCON[7:4] DVDD_REG_AD LOAD02 Nx SWITCHES NSWFULLCON OR SWCON[11:8] LOAD04 TSWFULLCON OR SWCON[15:12] HSTIACON[1:0] HIGH SPEED SELECTS SOURCE Tx SWITCHES TRANSIMPEDANCE...

  • Page 157: Ac Impedance Measurement While Maintaining Dc Bias To The Sensor

    ADuCM355 Hardware Reference Manual UG-1262 Exiting Cyclic Voltammetry Mode When exiting voltammetry mode to return to biasing the sensor normally or to resume taking dc measurements, take care to minimize the sensor settling time, as follows: Before adjusting the switches for a normal dc bias, reconfigure the low power DAC outputs to their required dc levels. Write to the LPDACDAT0 register or the LPDACDAT1 register.
  • Page 158 UG-1262 ADuCM355 Hardware Reference Manual After turning on the high speed DAC, calibrate the high speed DAC output if necessary (optional). The high speed DAC can be calibrated to remove the offset error by setting the output code to 0x800, as follows: ...
  • Page 159 ADuCM355 Hardware Reference Manual UG-1262 C = 0.1µF C = 0.1µF VZERO0 VBIAS0 VBIAS0 DUAL LPTIASWx[13] = 1 OUTPUTS LPTIASWx[12] = 1 12-BIT VZERO0 DACP LOW POWER LOOP: 12-BIT LPTIASWX = 0x302C Dx SWITCHES: WAVE DACN NORMAL CLOSE DR0 EXCITATION...
  • Page 160 UG-1262 ADuCM355 Hardware Reference Manual C = 0.1µF C = 0.1µF VZERO0 VBIAS0 VBIAS0 DUAL LPTIASWx[13] = 1 OUTPUTS LPTIASWx[12] = 1 12-BIT VDAC VZERO0 DACP LOW POWER 12-BIT Dx SWITCHES: LOOP: WAVE DACN CLOSE D5 LPTIASWx = EXCITATION OPEN OTHER...
  • Page 161 ADuCM355 Hardware Reference Manual UG-1262 C = 0.1µF C = 0.1µF VZERO0 VBIAS0 VBIAS0 DUAL LPTIASW[13] = 1 OUTPUTS LPTIASW[12] = 1 12-BIT DACP VZERO0 12-BIT LOW POWER WAVE DACN Dx SWITCHES: LOOP: EXCITATION CLOSE D5 LPTIASWx = OPEN OTHER...
  • Page 162 UG-1262 ADuCM355 Hardware Reference Manual where: V(s) is the signal voltage. I(s) is the calibration current. (magnitude) is the magnitude of the impedance of the calibration. Therefore,   (11) In Step 2,  (12)  RLOAD  RLOAD where: is the impedance of the sensor and Load Resistor 2.

  • Page 163: Dma Controller

    ADuCM355 Hardware Reference Manual UG-1262 DMA CONTROLLER The DMA controller is used to perform data transfer tasks between peripherals and memory locations to offload these tasks from the microcontroller unit (MCU). Data can be moved quickly by the DMA without CPU actions, keeping the CPU free for other operations.

  • Page 164: Dma Architectural Concepts

    UG-1262 ADuCM355 Hardware Reference Manual Program Flow After performing the following steps, the data FIFO issues DMA requests whenever the FIFO receives data. If the number of bytes transferred matches the value specified by Bits[13:4] of the control data configuration register (CFG), the DMA_DONE internal interrupt is asserted.

  • Page 165: Source Data End Pointer

    ADuCM355 Hardware Reference Manual UG-1262 Table 190. Memory Map of Primary and Alternate DMA Structures Primary Structures Alternate Structures Channel Number Register Description Offset Address Register Description Offset Address Channel 23 Reserved, set to 0 0x17C Reserved, set to 0...

  • Page 166: Control Data Configuration

    UG-1262 ADuCM355 Hardware Reference Manual CONTROL DATA CONFIGURATION For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller. Table 193. CHNL_CFG Control Data Configuration Source Bit(s) Name Data Width Setting Description...

  • Page 167: Dma Priority

    ADuCM355 Hardware Reference Manual UG-1262 Source Bit(s) Name Data Width Setting Description [17:14] R_POWER DMA Transfers Before Rearbitration. Set these bits to control the number of DMA transfers can occur before the controller rearbitrates. These bits must be set to 0000 for all DMA transfers involving peripherals.
  • Page 168 UG-1262 ADuCM355 Hardware Reference Manual Basic (CHNL_CFG, Bits[2:0] = 001) In basic mode, the controller can be configured to use either the primary or alternate data structure. The peripheral must present a request for every data transfer. After the channel is enabled, when the controller receives a request, it performs the following operations: The controller performs a transfer.
  • Page 169 ADuCM355 Hardware Reference Manual UG-1262 TASK A: PRIMARY, CYCLE_CTRL = 011, 2 = 4, N = 6 TASK A SOFTWARE REQUEST DMA_DONE[C] TASK B: ALTERNATE, CYCLE_CTRL = 011, 2 = 4, N = 12 TASK B SOFTWARE REQUEST AUTOMATIC REQUESTS...
  • Page 170 UG-1262 ADuCM355 Hardware Reference Manual Memory Scatter Gather (CHNL_CFG, Bits[2:0] = 100 or 101) In memory scatter gather mode, the controller must be configured to use both the primary and alternate data structures. The controller uses the primary data structure to program the control configuration for the alternate data structure. The alternate data structure is used for actual data transfers, which are similar to an autorequest DMA transfer.
  • Page 171 ADuCM355 Hardware Reference Manual UG-1262 PRIMARY ALTERNATE COPY FROM A REQUEST IN MEMORY TO ALTERNATE AUTOMATIC REQUESTS N = 3, 2 TASK A AUTOMATIC REQUESTS COPY FROM B IN MEMORY TO ALTERNATE AUTOMATIC REQUESTS TASK B AUTOMATIC REQUESTS N = 8, 2...
  • Page 172 UG-1262 ADuCM355 Hardware Reference Manual Table 195. CHNL_CFG for Primary Data Structure in Peripheral Scatter Gather Mode, CHNL_CFG, Bits[2:0] = 110 Bit(s) Name Description [31:30] DST_INC Set to 10, configures the controller to use word increments for the address. [29:28] Reserved Undefined.

  • Page 173: Dma Interrupts And Exceptions

    ADuCM355 Hardware Reference Manual UG-1262 DMA INTERRUPTS AND EXCEPTIONS Error Management The DMA controller generates an error interrupt to the core when a DMA error occurs. A DMA error can occur due to a bus error or an invalid descriptor fetch. A bus error can occur when fetching the descriptor or performing a data transfer. A bus error can occur when a read from or a write to a reserved address location occurs.

  • Page 174: Endian Operation

    UG-1262 ADuCM355 Hardware Reference Manual 0xFFFF 0xFFFF 0xFFFF 0xFFFF FIRST DATA SOURCE SOURCE LAST DATA LAST DATA POINTER POINTER LAST DATA LAST DATA FIRST DATA FIRST DATA FIRST DATA 0x0000 0x0000 0x0000 0x0000 SRC_DEC = 0 DST_DEC = 0 SRC_DEC = 0...

  • Page 175: Dma Master Enable

    ADuCM355 Hardware Reference Manual UG-1262 Whenever a channel is disabled, based on the current state of the DMA controller, the channel does one of the following:  If the user disables the channel and there is no request pending for that channel, it is disabled immediately.

  • Page 176: Register Summary: Dma

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: DMA Table 196. DMA Register Summary Address Name Description Reset Access 0x40010000 STAT Status 0x00180000 0x40010004 Configuration 0x00000000 0x40010008 PDBPTR Channel primary control data base pointer 0x00000000 0x4001000C ADBPTR Channel alternate control data base pointer...

  • Page 177: Register Details: Dma

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: DMA STATUS REGISTER Address: 0x40010000, Reset: 0x00180000, Name: STAT Table 197. Bit Descriptions for STAT Bits Bit Name Settings Description Reset Access [31:21] Reserved Reserved. 0x000 [20:16] CHANM1 Number of Available DMA Channels Minus 1. With 24 channels available, the register 0x18 reads back 0x17.

  • Page 178: Channel Software Request Register

    UG-1262 ADuCM355 Hardware Reference Manual CHANNEL SOFTWARE REQUEST REGISTER Address: 0x40010014, Reset: 0x00000000, Name: SWREQ The SWREQ register enables the generation of a software DMA request. Each bit of the register represents the corresponding channel number in the DMA controller. M is the number of DMA channels.

  • Page 179: Channel Enable Set Register

    ADuCM355 Hardware Reference Manual UG-1262 CHANNEL ENABLE SET REGISTER Address: 0x40010028, Reset: 0x00000000, Name: EN_SET Table 204. Bit Descriptions for EN_SET Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Enable DMA Channels. This register allows the enabling of DMA channels.

  • Page 180: Channel Primary Alternate Clear Register

    UG-1262 ADuCM355 Hardware Reference Manual CHANNEL PRIMARY ALTERNATE CLEAR REGISTER Address: 0x40010034, Reset: 0x00000000, Name: ALT_CLR The ALT_CLR write only register enables the user to configure the appropriate DMA channel to use the primary control data structure. Each bit of the register represents the corresponding channel number in the DMA controller. The DMA controller sets and clears these bits automatically as necessary for ping pong, memory scatter gather, and peripheral scatter gather transfers.

  • Page 181: Bus Error Clear Register

    ADuCM355 Hardware Reference Manual UG-1262 BUS ERROR CLEAR REGISTER Address: 0x40010048, Reset: 0x00000000, Name: ERR_CLR Table 210. Bit Descriptions for ERR_CLR Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Bus Error Status. This register is used to read and clear the DMA bus error status.

  • Page 182: Channel Bytes Swap Enable Set Register

    UG-1262 ADuCM355 Hardware Reference Manual CHANNEL BYTES SWAP ENABLE SET REGISTER Address: 0x40010800, Reset: 0x00000000, Name: BS_SET Table 213. Bit Descriptions for BS_SET Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Byte Swap Status. This register is used to configure a DMA channel to use byte 0x000000 swap.

  • Page 183: Channel Source Address Decrement Enable Clear Register

    ADuCM355 Hardware Reference Manual UG-1262 CHANNEL SOURCE ADDRESS DECREMENT ENABLE CLEAR REGISTER Address: 0x40010814, Reset: 0x00000000, Name: SRCADDR_CLR Table 216. Bit Descriptions for SRCADDR_CLR Bits Bit Name Settings Description Reset Access [31:24] Reserved Reserved. 0x00 [23:0] CHAN Disable Source Address Decrement. This register enables the user to configure a 0x000000 DMA channel to use the default source address in increment mode.

  • Page 184: Fifo Configuration Register

    UG-1262 ADuCM355 Hardware Reference Manual FIFO CONFIGURATION REGISTER Address: 0x400C2008, Reset: 0x00001010, Name: FIFOCON Table 219. Bit Descriptions for FIFOCON Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. [15:13] DATAFIFOSRCSEL Selects the Source for the Data FIFO. 000, 001, ADC data.

  • Page 185: Flash Controller

    ADuCM355 Hardware Reference Manual UG-1262 FLASH CONTROLLER FLASH CONTROLLER FEATURES ADuCM355 processor includes 128 kB of embedded flash memory available for access through the flash controller. The embedded flash has a 72-bit wide data bus, providing two 32-bit words of data and one corresponding 8-bit ECC byte per access.

  • Page 186: Flash Memory Structure

    Information Space Information space is reserved for use by Analog Devices and generally stores a bootloader (kernel), several trim and calibration values, and other device specific metadata. All but the top 128 bytes of information space are readable by user code, but attempted erasures and writes are denied.
  • Page 187 ADuCM355 Hardware Reference Manual UG-1262 INFORMATION SPACE 0x7FF RESERVED 0x7FC RESERVED RANGE 0x780 RESERVED 128 BYTES OF PROTECTED DATA INPUT INTO SPACE. ALL OTHER INFORMATION SPACE ADDRESSES ARE READ ONLY. 0x000 Figure 51. Information Space User Accessible Area User Space Metadata User space is the portion of flash memory intended for user data and program code.

  • Page 188: Flash Access

    UG-1262 ADuCM355 Hardware Reference Manual FLASH ACCESS Flash memory can be read, written, and erased by user code. Read access is provided through the cache controller using two AHB ports (as shown in Figure 53): ICode for instructions and DCode for data. Write access is provided through keyhole writes using APB control of memory mapped registers.

  • Page 189: Keyhole Writes

    ADuCM355 Hardware Reference Manual UG-1262 KEYHOLE WRITES A keyhole write is an indirect write operation wherein user code programs memory mapped registers with a target address and data values, then commands the flash controller to perform a write operation in the background. The flash controller supports write access to the flash memory only through keyhole writes.

  • Page 190: Dma Writes

    In the event of an information space integrity check failure, it is expected that the device has failed. Dispose the device or return the device to Analog Devices for failure analysis. If the information space integrity check does not pass, the flash controller enters a special purpose debugging mode.
  • Page 191 Write protection is a user feature that enables blocks of user space pages to be protected against all write or erase commands. Write protection can be set by the user at run time, or by an Analog Devices bootloader. If protection is set by the user, the user stores the desired value in flash for the bootloader to consume during start-up.

  • Page 192: Key Register

    UG-1262 ADuCM355 Hardware Reference Manual If immediate protection is required, user code must also write the same values to the WRPROT register. When writing the WRPROT metadata, consider including write protection of the most significant page, which protects the metadata from a page erase or other modification.

  • Page 193: Clock And Timings

    ADuCM355 Hardware Reference Manual UG-1262 User Key This key serves to prevent accidental access to some flash features and addresses. The key value is 0x676C7565. This key must be entered to run protected user commands (erase page, sign, mass erase, and abort) or to enable write access to the UCFG register. When entered, the key remains valid until an incorrect value is written to the key register, or a command is written to the CMD register.

  • Page 194: Flash Operating Modes

    UG-1262 ADuCM355 Hardware Reference Manual FLASH OPERATING MODES The flash memory used by the ADuCM355 processor supports the following power optimizing features. Sleep Mode The user code can put the flash IP into a low power sleep mode by writing the sleep command to the CMD register. The flash controller wakes the flash IP from sleep automatically on the first flash access following a sleep command.

  • Page 195: Register Summary: Flash Cache Controller (Flcc)

    ABORT_EN_LO IRQ abort enable (lower bits) 0x00000000 0x40018040 ABORT_EN_HI IRQ abort enable (upper bits) 0x00000000 0x40018044 ECC_CFG ECC configuration 0x00000002 0x40018048 ECC_ADDR ECC status (address) 0x00000000 0x40018050 ADI_POR_SEC Analog Devices flash security 0x00000000 Rev. B | Page 195 of 312...

  • Page 196: Register Details: Flash Cache Controller (Flcc)

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC) STATUS REGISTER Address: 0x40018000, Reset: 0x00000000, Name: STAT This register provides information on current command states, error detection, and correction. Table 224. Bit Descriptions for STAT Bits Bit Name...
  • Page 197 ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access [10:9] ECCRDERR ECC IRQ Cause. This field reports the cause of recently generated interrupts. R/W1C The controller can be configured to generate interrupts for 1-bit or 2-bit ECC events by writing the appropriate values to IEN, Bits[7:6].

  • Page 198: Interrupt Enable Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access CMDCOMP Command Complete. This bit asserts when a command completes. It R/W1C automatically clears when a new command is requested. Following a POR, the flash controller performs a number of operations, such as verifying the integrity of code in information space.

  • Page 199: Command Register

    ADuCM355 Hardware Reference Manual UG-1262 COMMAND REGISTER Address0x40018008, Reset: 0x00000000, Name: CMD Write this register to execute a specified command. The user key must first be written to the key register for most command requests to be honored. See the Key Register section for details.

  • Page 200: Write Address Register

    UG-1262 ADuCM355 Hardware Reference Manual WRITE ADDRESS REGISTER Address: 0x4001800C, Reset: 0x00000000, Name: KH_ADDR This register writes the byte address of any byte of a 64-bit, dual-word flash location to be targeted by a write command. All writes target 64-bit, dual-word elements in the flash array. User code can mask byte data to emulate byte, half word, or word writes. Flash IP specifications warn against writing to any location more than twice between erasures.

  • Page 201: Upper Page Address Register

    Integrity section). By default, the relevant location in flash is 0x3FFF0 (the fourth most significant word in user space) but can be relocated by the Analog Devices bootloader. Alternatively, user code can assert protection at run time for any unprotected blocks by directly writing this register. Blocks can have protection added but cannot have protection removed, and changes are lost on reset.

  • Page 202: Signature Register

    Hardware Reference Manual All write protection is cleared on a POR, but the Analog Devices bootloader reasserts write protection (as defined by the WRPROT word) in user space before enabling user access to the flash array. Removing write protection can only be performed by an erase page command of the most significant page in user space (provided that page is not currently protected) or by a mass erase command.

  • Page 203: Irq Abort Enable (Lower Bits) Register

    ADuCM355 Hardware Reference Manual UG-1262 IRQ ABORT ENABLE (LOWER BITS) REGISTER Address: 0x4001803C, Reset: 0x00000000, Name: ABORT_EN_LO Table 237. Bit Descriptions for ABORT_EN_LO Bits Bit Name Settings Description Reset Access [31:0] VALUE[31:0] System IRQ Abort Enable. To allow a system interrupt to abort an ongoing flash command, write 1 to the bit in this register corresponding with the desired system IRQ number.

  • Page 204: Analog Devices Flash Security Register

    UG-1262 ADuCM355 Hardware Reference Manual ANALOG DEVICES FLASH SECURITY REGISTER Address: 0x40018050, Reset: 0x00000000, Name: ADI_POR_SEC This register resets only after a POR or an external reset. Table 241. Bit Descriptions for ADI_POR_SEC Bits Bit Name Settings Description Reset Access...

  • Page 205: Sram

    ADuCM355 Hardware Reference Manual UG-1262 SRAM This section provides an overview of the SRAM functionality of the ADuCM355 processor. For details about the SRAM_INITSTAT, SRAM_CTL, and SRAMRET registers, refer to the Register Summary: Power Management Unit section. This memory space contains the application instructions and constant data that must be executed in real time. It supports read and write access via the Cortex-M3 core and read and write DMA access by system peripherals.

  • Page 206: Instruction Vs. Data Sram

    UG-1262 ADuCM355 Hardware Reference Manual  When the cache controller is enabled, 4 kB of the instruction SRAM is reserved for cache data. Those 4 kB of cache data are not retained in hibernate mode.  Parity bit error detection (optional) is available on all SRAM memories. Two parity bits are associated with each 32-bit word. Parity check can be configured to be enabled or disabled in different memory regions.
  • Page 207 ADuCM355 Hardware Reference Manual UG-1262 Initialization of more SRAM banks, where parity is enabled, can be achieved at any time by writing to the SRAM_CTL register. Set the appropriate SRAM_CTL, Bits[5:0] for SRAM banks that need parity to be enabled to 1. Also, set SRAM_CTL, Bit 13 to 1. SRAM_CTL, Bit 13 is autocleared to 0 after being written and triggers the initialization sequence.

  • Page 208: Cache

    UG-1262 ADuCM355 Hardware Reference Manual CACHE INITIALIZATION IN CACHE AND INSTRUCTION SRAM Enabling the cache provides a significant performance increase for applications executing from flash. Cache memory coexists with SRAM. When cache is enabled, part of the SRAM is allocated to the cache memory, and as such, cache memory cannot be used for other purposes.

  • Page 209: Register Summary: Cache (Flcc_Cache)

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: CACHE (FLCC) Table 242. FLCC Register Summary Address Name Description Reset Access 0x40018058 STAT Cache status 0x00000000 0x4001805C SETUP Cache setup 0x00000000 0x40018060 Cache key 0x00000000 Rev. B | Page 209 of 312...

  • Page 210: Register Details: Cache (Flcc_Cache)

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: CACHE (FLCC) CACHE STATUS REGISTER Address: 0x40018058, Reset: 0x00000000, Name: STAT Table 243. Bit Descriptions for STAT Bits Bit Name Settings Description Reset Access [31:1] Reserved Reserved. 0x0000000 ICEN Instruction Cache Enable. Disabled. All AHB accesses take place via flash memory.

  • Page 211: Silicon Identification

    ADuCM355 Hardware Reference Manual UG-1262 SILICON IDENTIFICATION The digital and analog die of the ADuCM355 contain a chip ID and hardware revision register that can be read by software to allow users to determine the current revision of the silicon. The automated test equipment (ATE) test program, kernel revisions, and unique chip ID number can be read from the read only locations detailed in Table 246.

  • Page 212: Register Summary: System (Digital Die)

    Hardware Reference Manual REGISTER SUMMARY: SYSTEM (DIGITAL DIE) Table 247. System Register Summary Address Name Description Reset Access 0x40002020 ADIID Analog Devices identification (digital die) 0x4144 0x40002024 CHIPID Chip identifier (digital die) 0x0284 0x40002040 SWDEN Serial wire debug enable 0x6E65 Table 248.

  • Page 213: Register Details: System (Digital Die)

    Reset Access [15:0] VALUE Analog Devices Identification. Reads a fixed value of 0x4144 to indicate to debuggers that 0x4144 they are connected to an Analog Devices implemented Cortex-based device. CHIP IDENTIFIER (DIGITAL DIE) REGISTER Address: 0x40002024, Reset: 0x0284, Name: CHIPID Chip identification for the digital die.

  • Page 214: Digital Inputs And Outputs

    UG-1262 ADuCM355 Hardware Reference Manual DIGITAL INPUTS AND OUTPUTS DIGITAL INPUTS AND OUTPUTS FEATURES ADuCM355 features multiple bidirectional GPIO pins (GPIOx/PWMx). Most of the GPIO pins have multiple functions, configurable by user code. On power-up, these pins are configured as tristate. There are three 16-bit wide ports. However, not all bits on some ports are accessible.

  • Page 215: Digital Inputs And Outputs Operation

    ADuCM355 Hardware Reference Manual UG-1262 DIGITAL INPUTS AND OUTPUTS OPERATION Each digital input and output is configured, read, and written independent of the other bits. General-Purpose Input Data (GPxIN) The status of the GPIO pins can be read via the GPxIN registers when configured as inputs by the GPxIEN registers.
  • Page 216 UG-1262 ADuCM355 Hardware Reference Manual Interrupt bits are cleared by writing 1 to the appropriate bit location in GPxINT. Writing 0 has no effect. If interrupts are enabled to the core (GPxIENA, GPxIENB), an interrupt GPxINT value of 1 results in an interrupt to the core. Clear this GPxINT bit during servicing of the interrupt.

  • Page 217: Digital Die Port Mux

    ADuCM355 Hardware Reference Manual UG-1262 DIGITAL DIE PORT MUX This block provides control over the GPIO functionality of specified pins. Some pins have the ability to work as a GPIO or perform other specific functions. Only configuration of the P2.4 pin of Port 2 is permitted. Attempted writes to other port pins are not allowed. Any blank cells in Table 255 are not applicable.

  • Page 218: Register Summary: Digital Inputs And Outputs

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: DIGITAL INPUTS AND OUTPUTS Table 257. Digital Die GPIO Register Summary Address Name Description Reset Access 0x40020000 GP0CON GPIO Port 0 configuration 0x00000000 0x40020004 GP0OEN GPIO Port 0 output enable 0x0000 0x40020008 GP0PE...
  • Page 219 ADuCM355 Hardware Reference Manual UG-1262 Table 258. AFE Die GPIO Register Summary Address Name Description Reset Access 0x400C0080 AFE GPIO port configuration 0x00 0x400C0084 AFE GPIO port output enable 0x400C0088 AFE GPIO port output pull-up and pull-down enable 0x400C008C AFE GPIO port input path enable...

  • Page 220: Register Details: Digital Inputs And Outputs

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: DIGITAL INPUTS AND OUTPUTS Not all bits are accessible to the user on every port. Inaccessible bits are reserved. See Table 255 for more details on the accessible bits. GPIO PORT CONFIGURATION REGISTERS...

  • Page 221: Gpio Port Input Path Enable Registers

    ADuCM355 Hardware Reference Manual UG-1262 GPIO PORT INPUT PATH ENABLE REGISTERS Address: 0x4002000C, Reset: 0x0000, Name: GP0IEN Address: 0x4002004C, Reset: 0x0002, Name: GP1IEN Address: 0x4002008C, Reset: 0x0000, Name: GP2IEN Table 262. Bit Descriptions for GP0IEN, GP1IEN, GP2IEN Bits Bit Name...

  • Page 222: Gpio Port Data Output Clear Registers

    UG-1262 ADuCM355 Hardware Reference Manual GPIO PORT DATA OUTPUT CLEAR REGISTERS Address: 0x4002001C, Reset: 0x0000, Name: GP0CLR Address: 0x4002005C, Reset: 0x0000, Name: GP1CLR Address: 0x4002009C, Reset: 0x0000, Name: GP2CLR Table 266. Bit Descriptions for GP0CLR, GP1CLR, GP2CLR Bits Bit Name...

  • Page 223: Gpio Port Interrupt B Enable Registers

    ADuCM355 Hardware Reference Manual UG-1262 GPIO PORT INTERRUPT B ENABLE REGISTERS Address: 0x4002002C, Reset: 0x0000, Name: GP0IENB Address: 0x4002006C, Reset: 0x0000, Name: GP1IENB Address: 0x400200AC, Reset: 0x0000, Name: GP2IENB Table 270. Bit Descriptions for GP0IENB, GP1IENB, GP2IENB Bits Bit Name...

  • Page 224: Afe Gpio Port Output Enable Register

    UG-1262 ADuCM355 Hardware Reference Manual AFE GPIO PORT OUTPUT ENABLE REGISTER Address: 0x400C0084, Reset: 0x0, Name: OEN Table 274. Bit Descriptions for OEN Bits Bit Name Settings Description Reset Access [15:3] Reserved Reserved. 0x0000 OEN1 Output Enable for AFE Die Clock to Digital Die. The AFE die Pad P2.2 is internally connected to the digital die internal Pad P1.10.

  • Page 225: Afe Gpio Port Data Output Set Register

    ADuCM355 Hardware Reference Manual UG-1262 AFE GPIO PORT DATA OUTPUT SET REGISTER Address: 0x400C0098, Reset: 0x0, Name: SET Table 279. Bit Descriptions for SET Bits Bit Name Settings Description Reset Access [15:2] Reserved Reserved. 0x0000 [1:0] Set Output High for the AFE Die Port Pins (GPIOx/PWMx). Set by user code to drive the corresponding GPIO high.

  • Page 226: I 2 C Serial Interface

    7-bit device addresses or a combination of one 10-bit address and two 7-bit addresses in the slave with repeated starts in master and slave modes. Other devices on the bus can enable clock stretching without causing any issues with the ADuCM355.
  • Page 227 ADuCM355 Hardware Reference Manual UG-1262 10-Bit Addressing This feature is enabled by setting SCTL, Bit 1 for master and slave mode. The 10-bit address of the slave is stored in the ID0 register and ID1 register, where the ID0 register contains the first byte of the address, and the R/W bit and the upper five bits must be programmed to 11110, as shown in Figure 58.

  • Page 228: I 2 C Operating Modes

    UG-1262 ADuCM355 Hardware Reference Manual Low = REQD_LOW_TIME/PCLK_PERIOD – 1 where REQD_LOW_TIME is the required low time period. For 100 kHz SCL operation with a low time of 5 μs, a high time of 5 μs, and a PCLK frequency of 26 MHz, High = (5 μs/(1/26,000,000)) −...
  • Page 229 ADuCM355 Hardware Reference Manual UG-1262 In the slave, if there is no valid data to transmit when the transmit shifter is loaded, the transmit underflow status bit asserts (MSTAT, Bit 12 or SSTAT, Bit 1). In slave mode, the transmit FIFO must be loaded with a byte before the falling edge of I2C_SCL and before the acknowledge or no acknowledge is asserted.
  • Page 230 It is recommended that all devices with an I C bus (including the ADuCM355) are fully powered up before any communications is started on the bus. Rev. B | Page 230 of 312...

  • Page 231: Register Summary: I C

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: I Table 282. I C Register Summary Address Name Description Reset Access 0x40003000 MCTL Master control 0x0000 0x40003004 MSTAT Master status 0x6000 0x40003008 Master receive data 0x0000 0x4000300C Master transmit data 0x0000 0x40003010...

  • Page 232: Register Details: I

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: I MASTER CONTROL REGISTER Address: 0x40003000, Reset: 0x0000, Name: MCTL Table 283. Bit Descriptions for MCTL Bits Bit Name Settings Description Reset Access [15:12] Reserved Reserved. MTXDMA Enable Master Transmit DMA Request. Disable DMA mode.

  • Page 233: Master Receive Data Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access MSTOP Stop Driven by this I C Master. Asserts when this I C master drives a stop condition on the I C bus. This bit, when asserted, can indicate a transaction completion, transmit underflow, receive overflow, or a no acknowledge by the slave.

  • Page 234: Master Transmit Data Register

    UG-1262 ADuCM355 Hardware Reference Manual MASTER TRANSMIT DATA REGISTER Address: 0x4000300C, Reset: 0x0000, Name: MTX Table 286. Bit Descriptions for MTX Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:0] VALUE Master Transmit. For test and debug purposes, when read, this register returns the byte that is currently being transmitted by the master.

  • Page 235: Serial Clock Period Divisor Register

    ADuCM355 Hardware Reference Manual UG-1262 SERIAL CLOCK PERIOD DIVISOR REGISTER Address: 0x40003024, Reset: 0x1F1F, Name: DIV Table 291. Bit Descriptions for DIV Bits Bit Name Settings Description Reset Access [15:8] HIGH Serial Clock High Time. This register controls the clock high time. The PCLK drives the timer.

  • Page 236: Slave I 2 C Status, Error, And Irq Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access ADR10EN Enabled 10-Bit Addressing. If this bit is clear, the slave can support four slave addresses, programmed in the ID0 register to the ID3 register. When this bit is set, 10-bit addressing is enabled.

  • Page 237: Slave Receive Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access STXREQ Slave Transmit Request. If SCTL, Bit 5 = 0, this bit is set when the direction bit for a transfer is received high. As long as the transmit FIFO is not full, this bit remains asserted.

  • Page 238: Second Slave Address Device Id Register

    UG-1262 ADuCM355 Hardware Reference Manual SECOND SLAVE ADDRESS DEVICE ID REGISTER Address: 0x40003040, Reset: 0x0000, Name: ID1 Table 298. Bit Descriptions for ID1 Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:0] Slave Device ID 1. ID1, Bits[7:1] are programmed with the device ID. ID1, Bit 0 is don't care.

  • Page 239: Master And Slave Shared Control Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access [3:2] SRXF Slave Receive FIFO Status. The status is a count of the number of bytes in a FIFO. FIFO empty. 1 bytes in the FIFO. 2 bytes in the FIFO.
  • Page 240 UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [3:0] Automatic Stretch Mode Control for Master. These bits control automatic stretch mode for master operation. These bits allow the master to hold the I2C_SCL line low and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition where the master indefinitely holds I2C_SCL low.

  • Page 241: Serial Peripheral Interfaces

    ADuCM355 Hardware Reference Manual UG-1262 SERIAL PERIPHERAL INTERFACES SPI FEATURES ADuCM355 integrates two complete hardware SPIs with the following standard features:  Serial clock phase mode and serial clock polarity mode.  LSB first transfer option.  Loopback mode. ...

  • Page 242: Spi Transfer Initiation

    UG-1262 ADuCM355 Hardware Reference Manual In master mode, the SPIx_CTL register controls the polarity and phase of the clock, and the bit rate is defined in the SPIx_DIV register as follows: PCLK  (25) SCLK   2 (1 SPIx DIV[5 : 0] where PCLK is the system clock divided by the factor set in CTL1, Bits[13:8].
  • Page 243 ADuCM355 Hardware Reference Manual UG-1262 In continuous mode, if SPIx_CNT, Bits[13:0] > 0 and SPIx_CNT, Bit 15 = 1, a read of the receive FIFO at the end of an SPI frame always initiates a new SPI frame. To stop SPI transfers at any given frame, clear the SPIx_CNT, Bit 15 before reading the final set of receive bytes.

  • Page 244: Spi Interrupts

    UG-1262 ADuCM355 Hardware Reference Manual Full Duplex Operation Simultaneous reads and writes are supported on the SPI. When implementing full duplex transfers in master mode, use the following procedure: Initiate a transfer sequence via a transmit on the P0.1/SPI0_MOSI pin and the P1.3/SPI1_MOSI pin. Set SPIx_CTL, Bit 6 = 1. If interrupts are enabled, interrupts are triggered when a transmit interrupt occurs but not when a byte is received.

  • Page 245: Spi Wire-Or'ed Mode

    ADuCM355 Hardware Reference Manual UG-1262 Underrun and Overflow Interrupts SPIx_STAT, Bit 7 and SPIx_STAT, Bit 4 generate SPI interrupts. When a transfer starts with no data in the transmit FIFO, SPIx_STAT, Bit 4 is set to indicate an underrun condition, which causes an interrupt. The interrupt and status bits are cleared upon a read of the status register.

  • Page 246: Spi And Power-Down Modes

    UG-1262 ADuCM355 Hardware Reference Manual SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency. SPI_CTL = 0x1043; //enables SPI in master mode and transmit mode, receive FIFO //flush enabled. SPI_CNT.VALUE = NUM_BYTES_TO transfer; //sets the number of bytes to transfer. SPI_DMA = 0x1;...

  • Page 247: Register Summary: Spi0/Spi1

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: SPI0/SPI1 Table 305. SPI Register Summary Address Name Description Reset Access 0x40004000 SPI0_STAT Status 0x0800 0x40004004 SPI0_RX Receive 0x0000 0x40004008 SPI0_TX Transmit 0x0000 0x4000400C SPI0_DIV Baud rate selection 0x0000 0x40004010 SPI0_CTL Configuration 0x0000...

  • Page 248: Register Details: Spi0/Spi1

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: SPI0/SPI1 STATUS REGISTERS Address: 0x40004000, Reset: 0x0800, Name: SPI0_STAT Address: 0x40024000, Reset: 0x0800, Name: SPI1_STAT Table 306. Bit Descriptions for SPI0_STAT, SPI1_STAT Bits Bit Name Settings Description Reset Access Detected an Edge on Ready Indicator for Flow Control. This bit indicates that there R/W1C was an active edge on the P0.3 line depending on the flow control mode.

  • Page 249: Receive Registers

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access TXDONE SPI Transmit Done in Read Command Mode. R/W1C Cleared to 0 when 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.

  • Page 250: Configuration Registers

    UG-1262 ADuCM355 Hardware Reference Manual CONFIGURATION REGISTERS Address: 0x40004010, Reset: 0x0000, Name: SPI0_CTL Address: 0x40024010, Reset: 0x0000, Name: SPI1_CTL Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL Bits Bit Name Settings Description Reset Access Reserved Reserved. CSRST Reset Mode for Chip Select Error Bit.

  • Page 251: Interrupt Configuration Registers

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access CPOL Serial Clock Polarity. Serial clock idles low. Serial clock idles high. CPHA Serial Clock Phase Mode. Serial clock pulses at the end of each serial bit transfer.

  • Page 252: Transfer Byte Count Registers

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [2:0] IRQMODE SPI IRQ Mode Bits. These bits configure when the transmit or receive interrupts occur in a transfer. For DMA receive transfer, these bits are 0b000. Transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs when 1 or more bytes have been received into the FIFO.

  • Page 253: Fifo Status Registers

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access TXEN Enable Transmit DMA Request. Disable transmit DMA interrupt. Enable transmit DMA interrupt. Enable DMA for Data Transfer. Set by user code to start a DMA transfer. Cleared by user code at the end of DMA transfer.

  • Page 254: Read Control Registers

    UG-1262 ADuCM355 Hardware Reference Manual READ CONTROL REGISTERS Address: 0x40004024, Reset: 0x0000, Name: SPI0_RD_CTL Address: 0x40024024, Reset: 0x0000, Name: SPI1_RD_CTL This register is only used in master mode. Table 315. Bit Descriptions for SPI0_RD_CTL, SPI1_RD_CTL Bits Bit Name Settings Description...

  • Page 255: Flow Control Registers

    ADuCM355 Hardware Reference Manual UG-1262 FLOW CONTROL REGISTERS Address: 0x40004028, Reset: 0x0000, Name: SPI0_FLOW_CTL Address: 0x40024028, Reset: 0x0000, Name: SPI1_FLOW_CTL This register is only used in master mode. Table 316. Bit Descriptions for SPI0_FLOW_CTL, SPI1_FLOW_CTL Bits Bit Name Settings Description...

  • Page 256: Uart Serial Interface

    UG-1262 ADuCM355 Hardware Reference Manual UART SERIAL INTERFACE UART OVERVIEW The UART peripheral is a full duplex UART, compatible with the industry-standard 16450 UART or 16550 UART. The UART is responsible for converting data between serial and parallel formats. The serial communication follows an asynchronous protocol, supporting various word lengths, stop bits, and parity generation options.
  • Page 257 ADuCM355 Hardware Reference Manual UG-1262 Interrupts The UART peripheral has one interrupt output to the interrupt controller for both receive and transmit interrupts. The COMIIR register must be read by the software to determine the cause of the interrupt. In DMA mode, the break interrupt is not available. When receiving in input or output mode, the interrupt is generated for the following cases: ...
  • Page 258 10 μs settling time after the first falling edge of the UART wake-up byte. This delay means that the first UART receive byte may not be read correctly by the ADuCM355, especially with UART baud rates ≥ 57,600.

  • Page 259: Register Summary: Uart

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: UART Table 320. UART Register Summary Address Name Description Reset Access 0x40005000 COMTX Transmit holding 0x0000 0x40005000 COMRX Receive buffer 0x0000 0x40005004 COMIEN Interrupt enabler 0x0000 0x40005008 COMIIR Interrupt identification 0x0001 0x4000500C COMLCR...

  • Page 260: Register Details: Uart

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: UART TRANSMIT HOLDING REGISTER Address: 0x40005000, Reset: 0x0000, Name: COMTX COMRX and COMTX share the same address although they are implemented as different registers. If these registers are written to, the user accesses the transmit holding register (COMTX). If these registers are read from, the user accesses the receive buffer register (COMRX).

  • Page 261: Interrupt Identification Register

    ADuCM355 Hardware Reference Manual UG-1262 INTERRUPT IDENTIFICATION REGISTER Address: 0x40005008, Reset: 0x0001, Name: COMIIR Table 324. Bit Descriptions for COMIIR Bits Bit Name Settings Description Reset Access [15:8] Reserved Reserved. [7:6] FEND FIFO Enabled. FIFO not enabled, 16450 UART mode.

  • Page 262: Modem Control Register

    UG-1262 ADuCM355 Hardware Reference Manual MODEM CONTROL REGISTER Address: 0x40005010, Reset: 0x0000, Name: COMMCR Table 326. Bit Descriptions for COMMCR Bits Bit Name Settings Description Reset Access [15:5] Reserved Reserved. LOOPBACK Loopback Mode. In loopback mode, the UART_SOUT is forced high. The modem signals are...

  • Page 263: Modem Status Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access Overrun Error. If set, this bit self clears after COMLSR is read. Receive data has not been overwritten. Receive data was overwritten by new data before COMRX was read.

  • Page 264: Fractional Baud Rate Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access FDMAMD FIFO DMA Mode. Receive DMA request is asserted when there is data in RBR in the COMRX register or the receive FIFO, and deasserts when RBR or the receive FIFO is empty. A transmit DMA request is asserted when THR in the COMTX register or the transmit FIFO is empty, and deasserts whenever data is written to the COMTX register.

  • Page 265: Uart Control Register

    ADuCM355 Hardware Reference Manual UG-1262 UART CONTROL REGISTER Address: 0x40005030, Reset: 0x0100, Name: COMCTL Table 334. Bit Descriptions for COMCTL Bits Bit Name Settings Description Reset Access [15:8] UART Revision ID. [7:5] Reserved Reserved. RXINV Invert Receiver Line. Do not invert receiver line (idling high).

  • Page 266: Autobaud Control Register

    UG-1262 ADuCM355 Hardware Reference Manual AUTOBAUD CONTROL REGISTER Address: 0x40005040, Reset: 0x0000, Name: COMACR Table 338. Bit Descriptions for COMACR Bits Bit Name Reserved Description Reset Access [15:12] Reserved Reserved. [11:8] Ending Edge Count. 0000 First edge. 0001 Second edge.

  • Page 267: Digital Die General-Purpose Timers

    ADuCM355 Hardware Reference Manual UG-1262 DIGITAL DIE GENERAL-PURPOSE TIMERS DIGITAL DIE GENERAL-PURPOSE TIMERS FEATURES ADuCM355 digital die integrates three identical general-purpose, 16-bit count up or count down timers: Timer 0, Timer 1, and Timer 2. These timers can be clocked from the 32 kHz internal low frequency oscillator, the PCLK, or the internal 26 MHz high frequency oscillator.
  • Page 268 UG-1262 ADuCM355 Hardware Reference Manual undefined results can occur. By default, the counter is reloaded automatically when generating the interrupt signal. If GPTx_CTL, Bit 7 is set to 1, the counter is also reloaded when user code writes GPTx_CLRINT, which allows user changes to GPTx_LOAD to take effect immediately instead of waiting until the next timeout.
  • Page 269 ADuCM355 Hardware Reference Manual UG-1262 Table 341. Capture Event Function Event Select Range Bits, CON0, Bits[12:8] Timer 0 Capture Source Timer 1 Capture Source Timer 2 Capture Source 0000 UART SYS_WAKE 0001 SYS_WAKE SPI0 Reserved 0010 Reserved Reserved Reserved 0011...

  • Page 270: Register Summary: General-Purpose Timers

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: GENERAL-PURPOSE TIMERS Table 342. Timer Register Summary Address Name Description Reset Access 0x40000000 GPT0_LOAD 16-bit synchronous load value 0x0000 0x40000004 GPT0_CURCNT 16-bit timer synchronous value 0x0000 0x40000008 GPT0_CTL Control 0x000A 0x4000000C GPT0_CLRINT Clear interrupt...

  • Page 271: Register Details: General-Purpose Timers

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: GENERAL-PURPOSE TIMERS 16-BIT SYNCHRONOUS LOAD VALUE REGISTERS Address: 0x40000000, Reset: 0x0000, Name: GPT0_LOAD Address: 0x40000400, Reset: 0x0000, Name: GPT1_LOAD Address: 0x40000800, Reset: 0x0000, Name: GPT2_LOAD Table 343. Bit Descriptions for GPT0_LOAD, GPT1_LOAD, GPT2_LOAD...

  • Page 272: Clear Interrupt Registers

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access MODE Timer Mode. This bit controls whether the timer runs in periodic or free running mode. In periodic mode, the up or down counter starts at the defined load value (GPTx_LOAD). In free running mode, the up or down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.

  • Page 273: 16-Bit Asynchronous Load Value Registers

    ADuCM355 Hardware Reference Manual UG-1262 16-BIT ASYNCHRONOUS LOAD VALUE REGISTERS Address: 0x40000014, Reset: 0x0000, Name: GPT0_ALOAD Address: 0x40000414, Reset: 0x0000, Name: GPT1_ALOAD Address: 0x40000814, Reset: 0x0000, Name: GPT2_ALOAD Table 348. Bit Descriptions for GPT0_ALOAD, GPT1_ALOAD, GPT2_ALOAD Bits Bit Name Settings...

  • Page 274: Analog Die General-Purpose Timers

    AFE PWM The AFE die in the ADuCM355 has a dedicated PWM output feature. The high period for the PWM is the difference between the values in the timer load register and either the PWMMAT0 register or PWMMATCH register. The low period for the PWM is the difference between either the PWMMAT0 register or PWMMATCH register and the overflow value 0xFFFF.

  • Page 275: Register Summary: Analog Die General-Purpose Timers

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS Table 351. AGPT0 Register Summary Address Name Description Reset Access 0x400C0D00 16-bit load value 0x0000 0x400C0D04 VAL0 16-bit timer value 0x0000 0x400C0D08 CON0 Control 0x000A 0x400C0D0C CLRI0 clear interrupt...

  • Page 276: Register Details: Analog Die General-Purpose Timers

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS 16-BIT LOAD VALUE REGISTER Address: 0x400C0D00, Reset: 0x0000, Name: LD0 Table 353. Bit Descriptions for LD0 Bits Bit Name Settings Description Reset Access Load Value. The up or down counter is periodically loaded with this value if periodic...

  • Page 277: Clear Interrupt Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access Count Up. Used to control whether the timer increments (counts up) or decrements (counts down) the up or down counter. Timer is set to count up. Timer is set to count down. Default.

  • Page 278: Status Register

    UG-1262 ADuCM355 Hardware Reference Manual STATUS REGISTER Address: 0x400C0D1C, Reset: 0x0000, Name: STA0 Table 359. Bit Descriptions for STA0 Bits Bit Name Settings Description Reset Access [15:9] Reserved Reserved. RSTCNT Counter Reset Occurring. Indicates that the counter is currently being reset due to an event detection.

  • Page 279: Interrupt Enable Register

    ADuCM355 Hardware Reference Manual UG-1262 INTERRUPT ENABLE REGISTER Address: 0x400C0D28, Reset: 0x0000, Name: INTEN Table 362. Bit Descriptions for INTEN Bits Bit Name Settings Description Reset Access [15:1] Reserved Reserved. INTEN Interrupt Enable. This value is used when the PWM is operating in match mode. The PWM output is asserted when the up or down counter is equal to this match value.

  • Page 280: Clear Interrupt Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access [6:5] Clock Select. Used to select a timer clock from the four available clock sources. AFE PCLK. AFE high power oscillator. AFE low frequency oscillator. External clock. Timer Enable. Used to enable and disable the timer. Clearing this bit resets the timer, including the CURCNT register.

  • Page 281: 16-Bit Timer Value, Asynchronous Register

    ADuCM355 Hardware Reference Manual UG-1262 16-BIT TIMER VALUE, ASYNCHRONOUS REGISTER Address: 0x400C0E18, Reset: 0x0000, Name: ACURCNT Only use when a synchronous clock source is selected (CTL, Bits[6:5] = 00). Table 368. Bit Descriptions for ACURCNT Bits Bit Name Settings Description...

  • Page 282: Afe Watchdog Timer

    UG-1262 ADuCM355 Hardware Reference Manual AFE WATCHDOG TIMER WATCHDOG TIMER FEATURES AND BLOCK DIAGRAM To satisfy the IEC 61508 standard requirement for separating the watchdog timer from all processor clock sources, the analog die watchdog timer is used to recover from an invalid software state. After the watchdog timer is enabled by user code, it requires periodic servicing to prevent it from forcing a reset of the processor.

  • Page 283: Register Summary: Afe Watchdog Timer

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER SUMMARY: AFE WATCHDOG TIMER Table 372. AFEWDT Register Summary Address Name Description Reset Access 0x400C0900 WDTLD Watchdog timer load value 0x1000 0x400C0904 WDTVALS Current count value 0x1000 0x400C0908 WDTCON Watchdog timer control 0x00C9 0x400C090C...

  • Page 284: Register Details: Afe Watchdog Timer

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER DETAILS: AFE WATCHDOG TIMER WATCHDOG TIMER LOAD VALUE REGISTER Address: 0x400C0900, Reset: 0x1000, Name: WDTLD Table 373. Bit Descriptions for WDTLD Bits Bit Name Settings Description Reset Access [15:0] LOAD Watchdog Timer Load Value. This user programmable value. is the value that the 0x1000 counter starts from before counting down to 0.

  • Page 285: Refresh Watchdog Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access WDT Interrupt Enable. Watchdog timer timeout creates a reset. Watchdog timer timeout creates an interrupt instead of a reset. PDSTOP Power Down Stop Enable. Continue counting when in hibernate mode. The watchdog timer continues its count down while in hibernate mode.

  • Page 286: Minimum Load Value Register

    UG-1262 ADuCM355 Hardware Reference Manual MINIMUM LOAD VALUE REGISTER Address: 0x400C091C, Reset: 0x0800, Name: WDTMINLD Watchdog timer minimum timeout period. Lower window limit. Table 378. Bit Descriptions for WDTMINLD Bits Bit Name Settings Description Reset Access [15:0] MIN_LOAD WDT Minimum Load Value. If software writes to WDTCLRI before the counter reaches 0x800 the MIN_LOAD value, a WDT reset or IRQ occurs.

  • Page 287: Digital Die Wake-Up Timer

    OVERVIEW The digital die WUT is the highest priority interrupt on the ADuCM355, as described in Table 41. The WUT is also one of four interrupt sources that can wake the digital die from hibernate mode. The WUT is clocked by the low frequency oscillator. The accuracy specifications of the low frequency oscillator deem this timer unsuitable for a real-time clock setup, although some register names indicate support for a true real-time clock.

  • Page 288: Wut Operating Modes

    UG-1262 ADuCM355 Hardware Reference Manual PROCESSOR CLOCK DOMAIN, CLOCK DOMAIN, FCLK AND PCLK 32kHz DIGITAL TRIM PRESCALER CRYSTAL INTERRUPT OSCILLATOR CONTROL FCLK TIMED CIRCUIT AND STATUS 32kHz IRQ TO NVIC (ANALOG) BASE CLOCK COUNT PRESCALED, GATED 32kHz RTC TIME BASE...
  • Page 289 ADuCM355 Hardware Reference Manual UG-1262 Ensuring No Communication Across WUT Power Boundary When Powering Down When the CPU has advance knowledge about a power-down, it must either check to confirm that there are no posted writes in the WUT awaiting execution or cancel all queued and executing posted writes in the WUT. Cancellation is achieved by writing a cancellation key of 0xA2C5 to the GWY register, which takes immediate effect.

  • Page 290: Register Summary: Digital Die Wake-Up Timer

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: DIGITAL DIE WAKE-UP TIMER Table 379. WUT Register Summary Address Name Description Reset Access 0x40001400 Control 0 0x03C4 0x40001404 Status 0 0x7F88 0x40001408 Status 1 0x0078 0x4000140C CNT0 Count 0 0x0000 0x40001410 CNT1...

  • Page 291: Register Details: Digital Die Wake-Up Timer

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER CONTROL 0 REGISTER Address: 0x40001400, Reset: 0x03C4, Name: CR0 CR0 is the primary of two control registers for the WUT, the other being CR1. All mainstream WUT operations are enabled and disabled by the CPU using CR0.

  • Page 292: Status 0 Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access MOD60ALMEN Enable WUT Modulo 60 Counting of Time Past a Modulo 60 Boundary. Enables the detection of the counter passing a value of 60, whereas MOD60ALMINTEN enables the generation of a resultant interrupt.
  • Page 293 ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access WSYNCALM0 Synchronization Status of Posted Writes to the ALM0 Register. WSYNCALM0 indicates if the effects of a posted write to ALM0 are visible to the CPU. Results of a posted write are not yet visible to the CPU.

  • Page 294: Status 1 Register

    UG-1262 ADuCM355 Hardware Reference Manual Bits Bit Name Settings Description Reset Access ISOINT WUT Power Domain Isolation Interrupt Source. ISOINT is a sticky interrupt source that R/W1C indicates whether the WUT has had to activate its power domain isolation barrier due to a power loss in the core.

  • Page 295: Count 0 Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access The WUT can accept new posted clearances of interrupt sources in SR0 located in the 32 kHz domain. A previously posted clearance of interrupt sources in SR0 and maintained in the 32 kHz domain is still awaiting execution.

  • Page 296: Alarm 0 Register

    UG-1262 ADuCM355 Hardware Reference Manual ALARM 0 REGISTER Address: 0x40001414, Reset: 0xFFFF, Name: ALM0 ALM0 contains the lower 16 bits of the prescaled nonfractional WUT alarm target time value, where the overall alarm is defined as ALM1, ALM0, and ALM2.

  • Page 297: Control 1 Register

    ADuCM355 Hardware Reference Manual UG-1262 CONTROL 1 REGISTER Address: 0x40001428, Reset: 0x01E0, Name: CR1 This register is a secondary control register that expands the level of WUT control, which is provided by CR0. CR1 allows additional sticky interrupt sources in SR2 to be enabled. These sources fan into the WUT peripheral interrupt to optionally...

  • Page 298: Status 2 Register

    UG-1262 ADuCM355 Hardware Reference Manual STATUS 2 REGISTER Address: 0x4000142C, Reset: 0xC000, Name: SR2 SR2 is a status register that further complements the status information provided by SR0 and SR1. SR2 contains sticky interrupt sources optionally enabled via the CR1 register. These interrupt sources alert the CPU when the WUT count has changed, when the prescaled gated clock that controls the advancement of the WUT count has activated, when a trim boundary has occurred, when the 32-bit WUT count has rolled over, and when the modulo 60 version of the WUT count has rolled over.

  • Page 299: Snapshot 0 Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access The WUT real-time count in CNT1, CNT0, and CNT2 has not risen due to a roll over. The WUT real-time count currently in CNT1, CNT0, and CNT2 has rolled over from a value at or within trimming distance of its maximum to a value at or within trimming distance of its minimum.

  • Page 300: Snapshot 1 Register

    UG-1262 ADuCM355 Hardware Reference Manual SNAPSHOT 1 REGISTER Address: 0x40001434, Reset: 0x0000, Name: SNAP1 SNAP1 is a sticky snapshot of the value of CNT1. It is updated at the same time as its counterparts, SNAP0 and SNAP2, thereby overwriting any previous value of SNAP1, SNAP0, and SNAP2. This updating and overwriting occurs when the CPU writes a snapshot request key of 0x7627 to the GWY register.

  • Page 301: Count 2 Register

    ADuCM355 Hardware Reference Manual UG-1262 Bits Bit Name Settings Description Reset Access [5:0] CNTMOD60 Modulo 60 Value of the WUT Count. CNTMOD60 is the modulo 60 value of the prescaled WUT count in CNT1 and CNT0. CNTMOD60 counts from 0 to 59 and then rolls over to 0 again.

  • Page 302: Status 6 Register

    UG-1262 ADuCM355 Hardware Reference Manual STATUS 6 REGISTER Address: 0x40001488, Reset: 0x7900, Name: SR6 SR6 is a status register that provides the unread status of snapshots of input capture channels, SNAP0, SNAP1, and SNAP2. Table 396. Bit Descriptions for SR6...

  • Page 303: Cyclic Redundancy Check

    ADuCM355 Hardware Reference Manual UG-1262 CYCLIC REDUNDANCY CHECK The CRC accelerator on the digital die computes the CRC for a block of memory locations on the digital die only. The exact memory location can be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a checksum that can be compared to an expected signature.
  • Page 304 UG-1262 ADuCM355 Hardware Reference Manual Polynomial The CRC accelerator supports the calculation of the CRC using any length polynomial. The polynomial must be written to the polynomial register. For MSB first implementation, omit the highest power while programming the CRC polynomial register and left justify the polynomial.
  • Page 305 ADuCM355 Hardware Reference Manual UG-1262 8-Bit Polynomial Programming for MSB First Calculation Polynomial: CRC-8-ATM + x + 1 = (1) 0000 0111 = 0x07 where the largest exponent (x term) is implied. Therefore, the polynomial is 0000 0111. When left justified in the polynomial register, the register format is detailed in Table 399.

  • Page 306: Crc Data Transfer

    UG-1262 ADuCM355 Hardware Reference Manual Reset and Hibernate Modes The CRC configuration bits are retained, except for the block enable bit (CTL, Bit 0). The block must be enabled again after exiting hibernate mode. The CRC polynomial and CRC result registers are retained after exiting hibernate mode. See Table 402 for details on the CRC registers after a reset and in hibernate mode.
  • Page 307 ADuCM355 Hardware Reference Manual UG-1262 Read the result register. This register contains the x-bit result in x MSB bits for MSB first and in x LSB bits for LSB first CRC calculations. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Step 1 to Step 5.

  • Page 308: Register Summary: Crc

    UG-1262 ADuCM355 Hardware Reference Manual REGISTER SUMMARY: CRC Table 404. CRC Register Summary Address Name Description Reset Access 0x40040000 CRC control register 0x10000000 0x40040004 IPDATA Input data word register 0x00000000 0x40040008 RESULT CRC result register 0x00000000 0x4004000C POLY Programmable CRC polynomial...

  • Page 309: Register Details: Crc

    ADuCM355 Hardware Reference Manual UG-1262 REGISTER DETAILS: CRC CRC CONTROL REGISTER Address: 0x40040000, Reset: 0x10000000, Name: CTL Table 405. Bit Descriptions for CTL Bits Bit Name Settings Description Reset Access [31:28] REVID Revision ID. [27:5] Reserved Reserved. W16SWP Word 16 Swap. This bit swaps 16-bit half words within a 32-bit word.

  • Page 310: Input Data Bits Register

    UG-1262 ADuCM355 Hardware Reference Manual INPUT DATA BITS REGISTER Address: 0x40040010 to 0x40040017 (Increments of 0x01), Reset: 0x00, Name: IPBITSN Table 409. Bit Descriptions for IPBITSN Bits Bit Name Settings Description Reset Access [7:0] DATA_BITS Input Data Bits. These fields are used to calculate CRC data byte from 1 bit to 7 bits of input data.

  • Page 311: Hardware Design Considerations

    ADuCM355 Hardware Reference Manual UG-1262 HARDWARE DESIGN CONSIDERATIONS TYPICAL SYSTEM CONFIGURATION DGND DVDD DVDD DVDD 470nF 470nF RESET RESET VDCDC_CAP1N VBAT 100nF VDCDC_CAP1P 10MΩ BM/P1.1 VDCDC_CAP2N 100nF RCAL0 VDCDC_CAP2P 200Ω VDCDC_CAPOUT RCAL1 470nF RC0_1 100nF ADuCM355 RC0_0 P0.11/ UART_SIN AIN1...

  • Page 312: Serial Wire Debug Interface

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